ADSP-21062/ADSP-21062L
Serial Ports
ADSP-21062
Max
ADSP-21062L
Max
Parameter
Min
Min
Units
External Clock
Timing Requirements:
tSFSE
TFS/RFS Setup Before TCLK/RCLK1
TFS/RFS Hold After TCLK/RCLK1, 2
Receive Data Setup Before RCLK1
Receive Data Hold After RCLK1
TCLK/RCLK Width
3.5
4
1.5
4
9
tCK
3.5
4
1.5
4
9
tCK
ns
ns
ns
ns
ns
ns
tHFSE
tSDRE
tHDRE
tSCLKW
tSCLK
TCLK/RCLK Period
Internal Clock
Timing Requirements:
tSFSI
TFS Setup Before TCLK1; RFS Setup
Before RCLK1
8
1
3
3
8
1
3
3
ns
ns
ns
ns
tHFSI
tSDRI
tHDRI
TFS/RFS Hold After TCLK/RCLK1, 2
Receive Data Setup Before RCLK1
Receive Data Hold After RCLK1
External or Internal Clock
Switching Characteristics:
tDFSE
RFS Delay After RCLK (Internally
Generated RFS)3
13
13
ns
ns
tHOFSE
RFS Hold After RCLK (Internally
Generated RFS)3
3
3
External Clock
Switching Characteristics:
tDFSE
TFS Delay After TCLK (Internally
Generated TFS)3
13
16
13
16
ns
tHOFSE
TFS Hold After TCLK (Internally
Generated TFS)3
3
5
3
5
ns
ns
ns
tDDTE
tHDTE
Transmit Data Delay After TCLK3
Transmit Data Hold After TCLK3
Internal Clock
Switching Characteristics:
tDFSI
TFS Delay After TCLK (Internally
Generated TFS)3
4.5
4.5
7.5
ns
tHOFSI
TFS Hold After TCLK (Internally
Generated TFS)3
–1.5
–1.5
0
ns
ns
ns
ns
tDDTI
tHDTI
tSCLKIW
Transmit Data Delay After TCLK3
Transmit Data Hold After TCLK3
TCLK/RCLK Width
7.5
0
(tSCLK/2) – 2.5
(tSCLK/2) + 2.5
(tSCLK/2) – 2.5 (tSCLK/2) + 2.5
Enable and Three-State
Switching Characteristics:
tDDTEN
tDDTTE
tDDTIN
tDDTTI
tDCLK
Data Enable from External TCLK3
4.25
0
4
ns
ns
ns
ns
ns
ns
Data Disable from External TCLK3
Data Enable from Internal TCLK3
Data Disable from Internal TCLK3
TCLK/RCLK Delay from CLKIN
SPORT Disable After CLKIN
10.5
16
0
3
7.5
22 + 3DT/8
17
22 + 3DT/8
17
tDPTR
Gated SCLK with External TFS
(Mesh Multiprocessing)4
Timing Requirements:
tSTFSCK
tHTFSCK
TFS Setup Before CLKIN
TFS Hold After CLKIN
5
5
ns
ns
tCK/2
tCK/2
External Late Frame Sync
Switching Characteristics:
tDDTLFSE Data Delay from Late External TFS or
External RFS with MCE = 1, MFD = 05
tDDTENFS Data Enable from late FS or MCE = 1,
MFD = 05
12.75
12.75
ns
ns
3.5
3.5
To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup
and hold, 2) data delay and data setup and hold, and 3) SCLK width.
REV. C
–36–
ADI [ ADI ]
