ADSP-21062/ADSP-21062L
Link Ports: 1 ؋
CLK Speed Operation
ADSP-21062
Max
ADSP-21062L
Parameter
Min
Min
Max
Units
Receive
Timing Requirements:
tSLDCL
tHLDCL
tLCLKIW
Data Setup Before LCLK Low
Data Hold After LCLK Low
LCLK Period (1 × Operation)
3
3
tCK
6
5
3
3
tCK
6
5
ns
ns
ns
ns
ns
tLCLKRWL LCLK Width Low
tLCLKRWH LCLK Width High
Switching Characteristics:
tDLAHC
tDLALC
tENDLK
tTDLK
LACK High Delay After CLKIN High
18 + DT/2
–3
5 + DT/2
28.5 + DT/2
13
18 + DT/2
–3
5 + DT/2
28.5 + DT/2
13
ns
ns
ns
ns
LACK Low Delay After LCLK High1
LACK Enable from CLKIN
LACK Disable from CLKIN
20 + DT/2
20 + DT/2
Transmit
Timing Requirements:
tSLACH LACK Setup Before LCLK High
tHLACH LACK Hold After LCLK High
18
–7
18
–7
ns
ns
Switching Characteristics:
tDLCLK
tDLDCH
tHLDCH
LCLK Delay After CLKIN (1 × operation)
Data Delay After LCLK High
Data Hold After LCLK High
15.5
2.5
15.5
2.5
ns
ns
ns
ns
ns
–3
–3
tLCLKTWL LCLK Width Low
tLCLKTWH LCLK Width High
(tCK/2) – 1
(tCK/2) + 1.25 (tCK/2) – 1
(tCK/2) – 1.5
(tCK/2) + 1.5
(tCK/2) + 1
(tCK/2) – 1.25 (tCK/2) + 1
tDLACLK
tENDLK
tTDLK
LCLK Low Delay After LACK High
LDAT, LCLK Enable After CLKIN
LDAT, LCLK Disable After CLKIN
(tCK/2) + 8.75 (3 × tCK/2) + 17 (tCK/2) + 8
(3 × tCK/2) + 17 ns
5 + DT/2
5 + DT/2
ns
20 + DT/2
20 + DT/2
ns
Link Port Service Request Interrupts: 1 × and
2 × Speed Operations
Timing Requirements:
tSLCK
tHLCK
LACK/LCLK Setup Before CLKIN Low2 10
10
2
ns
ns
LACK/LCLK Hold After CLKIN Low2
2
NOTES
1LACK will go low with tDLALC relative to rising edge of LCLK after first nibble is received. LACK will not go low if the receiver’s link buffer is not about to fill.
2Only required for interrupt recognition in the current cycle.
REV. C
–33–
ADI [ ADI ]
