ADSP-21062/ADSP-21062L
NOTES
1Referenced to sample edge.
2RFS hold after RCK when MCE = 1, MFD = 0 is 0 ns minimum from drive edge. TFS hold after TCK for late external TFS is 0 ns minimum from drive edge.
3Referenced to drive edge.
4Applies only to gated serial clock mode used for serial port system I/O in mesh multiprocessing systems.
5MCE = 1, TFS enable and TFS valid follow tDDTLFSE and tDDTENFS
.
DATA RECEIVE– INTERNAL CLOCK
DATA RECEIVE– EXTERNAL CLOCK
SAMPLE
EDGE
DRIVE
EDGE
DRIVE
EDGE
SAMPLE
EDGE
tSCLKIW
tSCLKW
RCLK
RCLK
tDFSE
tHOFSE
tDFSE
tHOFSE
tHFSE
tSFSI
tHFSI
tSFSE
RFS
DR
RFS
DR
tSDRE
tHDRE
tSDRI
tHDRI
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DATA TRANSMIT– INTERNAL CLOCK
DATA TRANSMIT– EXTERNAL CLOCK
SAMPLE
EDGE
DRIVE
EDGE
DRIVE
EDGE
SAMPLE
EDGE
tSCLKIW
tSCLKW
TCLK
TCLK
tDFSI
tHOFSI
tDFSE
tHOFSE
tSFSI
tHFSI
tHFSE
tSFSE
TFS
TFS
tDDTI
tDDTE
tHDTI
tHDTE
DT
DT
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DRIVE
EDGE
DRIVE
EDGE
TCLK / RCLK
TCLK (EXT)
DT
tDDTEN
tDDTTE
DRIVE
EDGE
DRIVE
EDGE
TCLK / RCLK
TCLK (INT)
tDDTIN
tDDTTI
DT
CLKIN
CLKIN
tHTFSCK
tDPTR
tSTFSCK
SPORT ENABLE AND
THREE-STATE
LATENCY
TCLK, RCLK
SPORT DISABLE DELAY
FROM INSTRUCTION
TFS (EXT)
TFS, RFS, DT
IS TWO CYCLES
tDCLK
NOTE: APPLIES ONLY TO GATED SERIAL CLOCK MODE WITH
EXTERNAL TFS, AS USED IN THE SERIAL PORT SYSTEM I/O FOR
MESH MULTIPROCESSING.
TCLK (INT)
RCLK (INT)
LOW TO HIGH ONLY
Figure 22. Serial Ports
–37–
REV. C
ADI [ ADI ]
