ADSP-21062/ADSP-21062L
DMA Handshake
transfer is controlled by ADDR31-0, RD, WR, MS3-0, and ACK
(not DMAG). For Paced Master mode, the Memory Read–Bus
Master, Memory Write–Bus Master, and Synchronous Read/
Write–Bus Master timing specifications for ADDR31-0, RD, WR,
MS3-0, SW, PAGE, DATA47-0, and ACK also apply.
These specifications describe the three DMA handshake modes.
In all three modes DMAR is used to initiate transfers. For hand-
shake mode, DMAG controls the latching or enabling of data
externally. For external handshake mode, the data transfer is
controlled by the ADDR31-0, RD, WR, SW, PAGE, MS3-0
,
ACK, and DMAG signals. For Paced Master mode, the data
ADSP-21062
ADSP-21062L
Max
Parameter
Min
Max
Min
Units
Timing Requirements:
tSDRLC
tSDRHC
tWDR
DMARx Low Setup Before CLKIN1
5
5
5
5
ns
ns
DMARx High Setup Before CLKIN1
DMARx Width Low
(Nonsynchronous)
6
2
6
2
ns
ns
ns
ns
ns
ns
tSDATDGL Data Setup After DMAGx Low2
tHDATIDG Data Hold After DMAGx High
tDATDRH Data Valid After DMARx High2
tDMARLL DMARx Low Edge to Low Edge
10 + 5DT/8
16 + 7DT/8
10 + 5DT/8
16 + 7DT/8
23 + 7DT/8
6
23 + 7DT/8
6
tDMARH
DMARx Width High
Switching Characteristics:
tDDGL
tWDGH
tWDGL
tHDGC
DMAGx Low Delay After CLKIN
DMAGx High Width
DMAGx Low Width
9 + DT/4
6 + 3DT/8
12 + 5DT/8
–2 – DT/8
8 + 9DT/16
0
15 + DT/4
6 – DT/8
9 + DT/4
6 + 3DT/8
12 + 5DT/8
–2 – DT/8
8 + 9DT/16
0
15 + DT/4
6 – DT/8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DMAGx High Delay After CLKIN
tVDATDGH Data Valid Before DMAGx High3
tDATRDGH Data Disable After DMAGx High4
7
2
7
2
tDGWRL
tDGWRH
tDGWRR
tDGRDL
tDRDGH
tDGRDR
tDGWR
WR Low Before DMAGx Low
DMAGx Low Before WR High
WR High Before DMAGx High
RD Low Before DMAGx Low
RD Low Before DMAGx High
RD High Before DMAGx High
DMAGx High to WR, RD, DMAGx
Low
–0.25
–0.25
10 + 5DT/8 + W
1 + DT/16
0
11 + 9DT/16 + W
0
10 + 5DT/8 + W
1 + DT/16
0
11 + 9DT/16 + W
0
3 + DT/16
2
3 + DT/16
2
3
3
5 + 3DT/8 + HI
5 + 3DT/8 + HI
17 + DT
ns
ns
tDADGH
tDDGHA
Address/Select Valid to DMAGx High 17 + DT
Address/Select Hold after DMAGx
High
–0.5
–1
ns
W = (number of wait states specified in WAIT register) × tCK
.
HI = tCK (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
NOTES
1Only required for recognition in the current cycle.
2tSDATDGL is the data setup requirement if DMARx is not being used to hold off completion of a write. Otherwise, if DMARx low holds off completion of the write, the
data can be driven tDATDRH after DMARx is brought high.
3tVDATDGH is valid if DMARx is not being used to hold off completion of a read. If DMARx is used to prolong the read, then tVDATDGH = 8 + 9DT/16 + (n × tCK) where
n equals the number of extra cycles that the access is prolonged.
4See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
REV. C
–31–
ADI [ ADI ]
