ADSP-21062/ADSP-21062L
Three-State Timing—Bus Master, Bus Slave, HBR, SBTS
These specifications show how the memory interface is disabled
(stops driving) or enabled (resumes driving) relative to CLKIN
and the SBTS pin. This timing is applicable to bus master tran-
sition cycles (BTC) and host transition cycles (HTC) as well as
the SBTS pin.
ADSP-21062
ADSP-21062L
Parameter
Min
Max
Min
Max
Units
Timing Requirements:
tSTSCK
tHTSCK
SBTS Setup Before CLKIN
SBTS Hold Before CLKIN
12 + DT/2
12 + DT/2
ns
ns
6 + DT/2
6 + DT/2
Switching Characteristics:
tMIENA Address/Select Enable After CLKIN
tMIENS
Strobes Enable After CLKIN1
tMIENHG HBG Enable After CLKIN
tMITRA Address/Select Disable After CLKIN
tMITRS
Strobes Disable After CLKIN1
tMITRHG HBG Disable After CLKIN
tDATEN
tDATTR
tACKEN
tACKTR
tADCEN
tADCTR
–1 – DT/8
–1.5 – DT/8
–1.5 – DT/8
–1.25 – DT/8
–1.5 – DT/8
–1.5 – DT/8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0 – DT/4
1.5 – DT/4
2.0 – DT/4
0 – DT/4
1.5 – DT/4
2.0 – DT/4
Data Enable After CLKIN2
Data Disable After CLKIN2
ACK Enable After CLKIN2
ACK Disable After CLKIN2
ADRCLK Enable After CLKIN
ADRCLK Disable After CLKIN
9 + 5DT/16
0 – DT/8
7.5 + DT/4
–1 – DT/8
–2 – DT/8
9 + 5DT/16
–0.5 – DT/8
7.5 + DT/4
–1 – DT/8
–2 – DT/8
7 – DT/8
6 – DT/8
8 – DT/4
7 – DT/8
6 – DT/8
8 – DT/4
tMTRHBG Memory Interface Disable Before
HBG Low3
tMENHBG Memory Interface Enable After
HBG High3
0 + DT/8
19 + DT
0 + DT/8
19 + DT
ns
ns
NOTES
1Strobes = RD, WR, SW, PAGE, DMAG.
2In addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write.
3Memory Interface = Address, RD, WR, MSx, SW, PAGE, DMAGx, BMS (in EPROM boot mode).
CLKIN
tSTSCK
tHTSCK
SBTS
tMITRA, tMITRS, tMITRHG
tMIENA, tMIENS, tMIENHG
MEMORY
INTERFACE
tDATTR
tDATEN
DATA
tACKTR
tACKEN
ACK
tADCEN
tADCTR
ADRCLK
Figure 19a. Three-State Timing (Bus Transition Cycle, SBTS Assertion)
HBG
tMTRHBG
tMENHBG
MEMORY
INTERFACE
MEMORY INTERFACE = ADDRESS, RD, WR, MSx, SW, PAGE, DMAGx. BMS (IN EPROM BOOT MODE)
Figure 19b. Three-State Timing (Host Transition Cycle)
REV. C
–30–
ADI [ ADI ]
