ADSP-21062/ADSP-21062L
Multiprocessor Bus Request and Host Bus Request
Use these specifications for passing of bus mastership between
multiprocessing ADSP-21062s (BRx) or a host processor
(HBR, HBG).
ADSP-21062
Max
ADSP-21062L
Max
Parameter
Min
Min
Units
Timing Requirements:
tHBGRCSV
tSHBRI
tHHBRI
tSHBGI
tHHBGI
tSBRI
HBG Low to RD/WR/CS Valid1
20 + 5DT/4
14 + 3DT/4
6 + DT/2
20 + 5DT/4
14 + 3DT/4
6 + DT/2
ns
ns
ns
ns
ns
ns
ns
ns
ns
HBR Setup Before CLKIN2
20 + 3DT/4
13 + DT/2
13 + DT/2
21 + 3DT/4
20 + 3DT/4
13 + DT/2
13 + DT/2
21 + 3DT/4
HBR Hold Before CLKIN2
HBG Setup Before CLKIN
HBG Hold Before CLKIN High
BRx, CPA Setup Before CLKIN3
BRx, CPA Hold Before CLKIN High
RPBA Setup Before CLKIN
RPBA Hold Before CLKIN
tHBRI
tSRPBAI
tHRPBAI
6 + DT/2
6 + DT/2
12 + 3DT/4
12 + 3DT/4
Switching Characteristics:
tDHBGO
tHHBGO
tDBRO
HBG Delay After CLKIN
7 – DT/8
7 – DT/8
7 – DT/8
7 – DT/8
ns
ns
ns
ns
ns
ns
HBG Hold After CLKIN
BRx Delay After CLKIN
BRx Hold After CLKIN
CPA Low Delay After CLKIN
CPA Disable After CLKIN
REDY (O/D) or (A/D) Low from CS
and HBR Low4
–2 – DT/8
–2 – DT/8
–2 – DT/8
–2 – DT/8
–2 – DT/8
–2 – DT/8
tHBRO
tDCPAO
tTRCPA
tDRDYCS
8 – DT/8
4.5 – DT/8
8 – DT/8
4.5 – DT/8
8.5
10
8.75
10
ns
ns
ns
tTRDYHG
tARDYTR
REDY (O/D) Disable or REDY (A/D)
High from HBG4
44 + 23DT/16
44 + 23DT/16
REDY (A/D) Disable from CS or
HBR High4
NOTES
1For first asynchronous access after HBR and CS asserted, ADDR31-0 must be a non-MMS value 1/2 tCK before RD or WR goes low or by tHBGRCSV after HBG goes
low. This is easily accomplished by driving an upper address signal high when HBG is asserted. See the “Host Processor Control of the ADSP-21062” section in the
ADSP-21062 SHARC User’s Manual, Second Edition.
2Only required for recognition in the current cycle.
3CPA assertion must meet the setup to CLKIN; deassertion does not need to meet the setup to CLKIN.
4(O/D) = open drain, (A/D) = active drive.
REV. C
–26–
ADI [ ADI ]
