ADSP-21062/ADSP-21062L
Asynchronous Read/Write—Host to ADSP-21062
drive the RD and WR pins to access the ADSP-21062’s internal
memory or IOP registers. HBR and HBG are assumed low for
this timing.
Use these specifications for asynchronous host processor accesses
of an ADSP-21062, after the host has asserted CS and HBR
(low). After HBG is returned by the ADSP-21062, the host can
ADSP-21062
Max
ADSP-21062L
Max
Parameter
Min
Min
Units
Read Cycle
Timing Requirements:
tSADRDL
tHADRDH
tWRWH
tDRDHRDY
tDRDHRDY
Address Setup/CS Low Before RD Low1
Address Hold/CS Hold Low After RD
RD/WR High Width
RD High Delay After REDY (O/D) Disable
RD High Delay After REDY (A/D) Disable
0
0
6
0
0
0
0
6
0
0
ns
ns
ns
ns
ns
Switching Characteristics:
tSDATRDY
tDRDYRDL
tRDYPRD
Data Valid Before REDY Disable from Low
2
2
ns
ns
REDY (O/D) or (A/D) Low Delay After RD Low
REDY (O/D) or (A/D) Low Pulse
Width for Read
10
8
10
8
45 + 21DT/16
2
45 + 21DT/16
2
ns
ns
tHDARWH
Data Disable After RD High
Write Cycle
Timing Requirements:
tSCSWRL
tHCSWRH
tSADWRH
tHADWRH
tWWRL
CS Low Setup Before WR low
0
0
5
2
7
6
0
0
5
2
7
6
ns
ns
ns
ns
ns
ns
CS Low Hold After WR high
Address Setup Before WR High
Address Hold After WR High
WR Low Width
tWRWH
RD/WR High Width
tDWRHRDY
WR High Delay After REDY
(O/D) or (A/D) Disable
0
5
1
0
5
1
ns
ns
ns
tSDATWH
tHDATWH
Data Setup Before WR High
Data Hold After WR High
Switching Characteristics:
tDRDYWRL REDY (O/D) or (A/D) Low Delay
After WR/CS Low
REDY (O/D) or (A/D) Low Pulse
Width for Write
10
10
ns
ns
tRDYPWR
15 + 7DT/16
1 + 7DT/16
15 + 7DT/16
tSRDYCK
REDY (O/D) or (A/D) Disable to CLKIN
8 + 7DT/16 1 + 7DT/16
8 + 7DT/16 ns
NOTE
1Not required if RD and address are valid tHBGRCSV after HBG goes low. For first access after HBR asserted, ADDR31-0 must be a non-MMS value 1/2 tCLK before RD
or WR goes low or by tHBGRCSV after HBG goes low. This is easily accomplished by driving an upper address signal high when HBG is asserted. See the “Host Proces-
sor Control of the ADSP-21062” section in the ADSP-21062 SHARC User’s Manual, Second Edition.
CLKIN
tSRDYCK
REDY (O/D)
REDY (A/D)
O/D = OPEN DRAIN, A/D = ACTIVE DRIVE
Figure 18a. Synchronous REDY Timing
REV. C
–28–
ADI [ ADI ]
