ADM1026
Table 97. Register 54h, AIN4 High Limit (Power-On Default FFh)
Bit
Name
R/W
Description
7–0
AIN4 High Limit
R/W
This register contains the high limit of the AIN4 analog input channel.
Table 98. Register 55h, AIN5 High Limit (Power-On Default FFh)
Bit
Name
R/W
Description
7–0
AIN5 High Limit
R/W
This register contains the high limit of the AIN5 analog input channel.
Table 99. Register 56h, AIN6 High Limit (Power-On Default FFh)
Bit
Name
R/W
Description
7–0
AIN6 High Limit
R/W
This register contains the high limit of the AIN6 analog input channel.
Table 100. Register 57h, AIN7 High Limit (Power-On Default FFh)
Bit
Name
R/W
Description
7–0
AIN7 High Limit
R/W
This register contains the high limit of the AIN7 analog input channel.
Table 101. Register 58h, AIN0 Low Limit (Power-On Default 00h)
Bit
Name
R/W
Description
7–0
AIN0 Low Limit
R/W
This register contains the low limit of the AIN0 analog input channel.
Table 102. Register 59h, AIN1 Low Limit (Power-On Default 00h)
Bit
Name
R/W
Description
7–0
AIN± Low Limit
R/W
This register contains the low limit of the AIN± analog input channel.
Table 103. Register 5Ah, AIN2 Low Limit (Power-On Default 00h)
Bit
Name
R/W
Description
7–0
AIN2 Low Limit
R/W
This register contains the low limit of the AIN2 analog input channel.
Table 104. Register 5Bh, AIN3 Low Limit (Power-On Default 00h)
Bit
Name
R/W
Description
7–0
AIN3 Low Limit
R/W
This register contains the low limit of the AIN3 analog input channel.
Table 105. Register 5Ch, AIN4 Low Limit (Power-On Default 00h)
Bit
Name
R/W
Description
7–0
AIN4 Low Limit
R/W
This register contains the low limit of the AIN4 analog input channel.
Table 106. Register 5Dh, AIN5 Low Limit (Power-On Default 00h)
Bit
Name
R/W
Description
7–0
AIN5 Low Limit
R/W
This register contains the low limit of the AIN5 analog input channel.
Table 107. Register 5Eh, AIN6 Low Limit (Power-On Default 00h)
Bit
Name
R/W
Description
7–0
AIN6 Low Limit
R/W
This register contains the low limit of the AIN6 analog input channel.
Table 108. Register 5Fh, AIN7 Low Limit (Power-On Default 00h)
Bit
Name
R/W
Description
7–0
AIN7 Low Limit
R/W
This register contains the low limit of the AIN7 analog input channel.
Table 109. Register 60h, FAN0 High Limit (Power-On Default FFh)
Bit
Name
R/W
Description
7–0
FAN0 High Limit
R/W
This register contains the high limit of the FAN0 tach channel.
Table 110. Register 61h, FAN1 High Limit (Power-On Default FFh)
Bit
Name
R/W
Description
7–0
FAN± High Limit
R/W
This register contains the high limit of the FAN± tach channel.
Rev. A | Page 5± of 56
ADI [ ADI ]
