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AD9865BCPZ1 参数 Datasheet PDF下载

AD9865BCPZ1图片预览
型号: AD9865BCPZ1
PDF下载: 下载PDF文件 查看货源
内容描述: 宽带调制解调器混合信号前端 [Broadband Modem Mixed-Signal Front End]
分类和应用: 调制解调器
文件页数/大小: 48 页 / 2209 K
品牌: ADI [ ADI ]
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AD9865  
specification is based on the 64-pin LFSCP having a thermal  
resistance, θJA, of 24oC/W with its heat slug soldered. (The θJA is  
30.8oC/W, if the heat slug remains unsoldered.) If a particular  
application’s maximum ambient temperature, TA, falls below  
85oC, the maximum allowable power dissipation can be deter-  
mined by the following equation:  
220  
210  
200  
190  
180  
170  
160  
150  
140  
130  
101 OR 111  
000  
001  
010  
P
MAX = 1.66 + (85 − TA)/24  
(13)  
011  
101  
100  
Assuming the IAMPs common-mode bias voltage is operating  
off the same analog supply as the AD9865, the following equa-  
tion can be used to calculate the maximum total current  
consumption, IMAX, of the IC:  
120  
20  
30  
40  
50  
60  
70  
80  
I
MAX = (PMAX PIAMP)/3.47  
(14)  
SAMPLE RATE (MSPS)  
Figure 83. AVDD Current vs. ADC Bias Setting and Sample Rate  
With an ambient temperature of up to 85°C, IMAX is 478 mA.  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
–54  
If the IAMP is operating off a different supply or in the voltage  
mode configuration, first calculate the power dissipated in the  
IAMP, PIAMP, using Equation 2 or Equation 5, and then  
recalculate IMAX, using Equation 14.  
–56  
–58  
–60  
–62  
–64  
–66  
–68  
–70  
–72  
–74  
THD-000  
THD-001  
THD-010  
THD-011  
THD-100  
THD-101  
Figure 78, Figure 79, Figure 81, and Figure 83 can be used to  
calculate the current consumption of the Rx and Tx paths for a  
given setting.  
SNR-000  
SNR-001  
SNR-010  
SNR-011  
SNR-100  
SNR-101  
MODE SELECT UPON POWER-UP AND RESET  
The AD9865 power-up state is determined by the logic levels  
appearing at the MODE and CONFIG pins. The MODE pin is  
used to select a half- or full-duplex interface by pin strapping it  
low or high, respectively. The CONFIG pin is used in conjunc-  
tion with the MODE pin to determine the default settings for  
the SPI registers as outlined in Table 10.  
20  
30  
40  
50  
60  
70  
80  
SAMPLE RATE (MSPS)  
Figure 84. SNR and THD Performance vs. fADC and ADC Bias Setting with  
RxPGA = 0 dB, fIN = 10 MHz, and AIN = −1 dBFS  
The intent of these particular default settings is to allow some  
applications to avoid using the SPI (disabled by pin-strapping  
A sine wave input is a standard and convenient method of  
analyzing the performance of a system. However, the amount of  
power reduction that is possible is application dependent, based  
on the nature of the input waveform (such as frequency content,  
peak-to-rms ratio), the minimum ADC sample, and the mini-  
mum acceptable level of performance. Thus, it is advisable that  
power-sensitive applications optimize the power bias setting of  
the Rx path using an input waveform that is representative of  
the application.  
high), thereby reducing implementation costs. For  
SEN  
example, setting MODE low and CONFIG high configures the  
AD9865 to be backward compatible with the AD9975, while  
setting MODE high and CONFIG low makes it backward  
compatible with the AD9875. Other applications must use the  
SPI to configure the device.  
RESET  
A hardware (  
pin) or software (Bit 5 of Register 0x00)  
reset can be used to place the AD9865 into a known state of  
operation as determined by the state of the MODE and  
CONFIG pins. A dc offset calibration and filter tuning routine  
is also initiated upon a hardware reset, but not with a software  
reset. Neither reset method flushes the digital interpolation  
filters in the Tx path. Refer to the Half-Duplex Mode and Full-  
Duplex Mode sections for information on flushing the digital  
filters.  
POWER DISSIPATION  
The power dissipation of the AD9865 can become quite high in  
full-duplex applications in which the Tx and Rx paths are si-  
multaneously operating with nominal power bias settings. In  
fact, some applications that use the IAMP may need to either  
reduce its peak power capabilities or reduce the power con-  
sumption of the Rx path, so that the devices maximum  
allowable power consumption, PMAX, is not exceeded.  
RESET  
A hardware reset can be triggered by pulsing the  
for a minimum of 50 ns. The SPI registers are instantly reset to  
their default settings upon going low, while the dc offset  
pin low  
PMAX is specified at 1.66 W to ensure that the die temperature  
does not exceed 125oC at an ambient temperature of 85oC. This  
RESET  
Rev. A | Page 42 of 48  
 
 
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