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AD9865BCPZ1 参数 Datasheet PDF下载

AD9865BCPZ1图片预览
型号: AD9865BCPZ1
PDF下载: 下载PDF文件 查看货源
内容描述: 宽带调制解调器混合信号前端 [Broadband Modem Mixed-Signal Front End]
分类和应用: 调制解调器
文件页数/大小: 48 页 / 2209 K
品牌: ADI [ ADI ]
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AD9865  
occur during undershoot or overshoot caused by ringing. If the  
signal traces cannot be kept shorter than about 1.5 inches, series  
termination resistors (33 Ω to 47 Ω) should be placed close to  
all digital signal sources. It is a good idea to series-terminate all  
clock signals at their source, regardless of trace length.  
form a differential pair and should be routed together as a pair.  
By keeping the traces adjacent to each other, noise coupled onto  
the signals appears as common mode and is largely rejected by  
the MxFE receive input. Keeping the driving point impedance  
of the receive signal low and placing any low-pass filtering of  
the signals close to the MxFE further reduces the possibility of  
noise corrupting these signals.  
The receive RX+ and RX− signals are the most sensitive signals  
on the entire board. Careful routing of these signals is essential  
for good receive path performance. The RX+ and RX− signals  
Rev. A | Page 45 of 48  
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