AD9865
occurs within 100 ns. The user-programmable delay for the Tx
path power-down is meant to match the pipeline delay of the
last Tx burst sample such that power-down of the TxDAC and
IAMP does not impact its transmission. A 5-bit field in Register 0x03
sets the delay from 0 to 31 TXCLK clock cycles, with the default
being 31 (0.62 µs with fTXCLK = 50 MSPS). The digital interpolation
filter is automatically flushed with midscale samples prior to
power-down, if the clock signal into the TXCLK pin is present
for 33 additional clock cycles after TXEN returns low. For an Rx
burst, the rising edge of TXEN is used to generate an internal
signal (with no delay) that powers up the Tx circuitry within 0.5 µs.
55
50
45
40
35
30
25
20
15
10
The Rx path power-on/power-off can be controlled by either
TXEN or RXEN by setting Bit 2 of Register 0x03. In the default
setting, the falling edge of TXEN powers up the Rx circuitry
within 2 µs, while the rising edge of TXEN powers down the Rx
circuitry within 0.5 µs. If RXEN is selected as the control signal,
then its rising edge powers up the Rx circuitry and the falling
edge powers it down. To disable the fast power-down of the Tx
and/or Rx circuitry, set Bit 1 and/or Bit 0 to 0.
0
1
2
3
4
5
6
7
8
9
10 11 12 13
I
(mA)
STANDING
Figure 78. Reduction in TxDAC’s Supply Current vs. Standing Current
65
60
4× INTERPOLATION
55
50
45
40
35
30
25
20
15
POWER REDUCTION OPTIONS
The power consumption of the AD9865 can be significantly
reduced from its default setting by optimizing the power
consumption versus performance of the various functional
blocks in the Tx and Rx signal path. On the Tx path, minimum
power consumption is realized when the TxDAC output is used
directly and its standing current, I, is reduced to as low as 1 mA.
Although a slight degradation in THD performance results at
reduced standing currents, it often remains adequate for most
applications, because the op amp driver typically limits the
overall linearity performance of the Tx path. The load resistors
used at the TxDAC outputs (IOUTP+ and IOUTP−) can be
increased to generate an adequate differential voltage that can
be further amplified via a power efficient op-amp-based driver
solution. Figure 78 shows how the supply current for the
TxDAC (Pin 43) is reduced from 55 mA to 14 mA as the
standing current is reduced from 12.5mA to 1.25 mA. Further
Tx power savings can be achieved by bypassing or reducing the
interpolation factor of the digital filter as shown in Figure 79.
2× INTERPOLATION
1× (HALF-DUPLEX ONLY)
20
30
40
50
60
70
80
INPUT DATA RATE (MSPS)
Figure 79. Digital Supply Current Consumption vs. Input Data Rate
(DVDD = DRVDD =3.3 V and fOUT = fDATA/10)
Power consumption on the Rx path can be achieved by reduc-
ing the bias levels of the various amplifiers contained within the
RxPGA and ADC. As previously noted, the RxPGA consists of
two CPGA amplifiers and one SPGA amplifier. The bias levels
of each of these amplifiers along with the ADC can be con-
trolled via Register 0x13, as shown in Table 24. The default
setting for 0x13 is 0x00.
Table 24. SPI Register for RxPGA and ADC Biasing
Address (Hex)
Bit
Description
0x07
(4)
ADC low power
CPGA bias adjust
SPGA bias adjust
ADC power bias adjust
0x13
(7:5)
(4:3)
(2:0)
Rev. A | Page 40 of 48
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