AD9865
210
205
200
195
190
185
180
175
170
Because the CPGA processes signals in the continuous time
domain, its performance vs. bias setting remains mostly
independent of the sample rate. Table 25 shows how the typical
current consumption seen at AVDD (Pins 35 and 40) varies as a
function of Bits (7:5), while the remaining bits are maintained at
their default settings of 0. Only four of the possible settings
result in any reduction in current consumption relative to the
default setting. Reducing the bias level typically results in a
degradation in the THD vs. frequency performance as shown in
Figure 80. This is due to a reduction of the amplifier’s unity gain
bandwidth, while the SNR performance remains relatively
unaffected.
01
00
10
11
20
30
40
50
60
70
80
Table 25. Analog Supply Current vs. CPGA Bias Settings at
fADC = 65 MSPS
ADC SAMPLE RATE (MSPS)
Figure 81. AVDD Current vs. SPGA Bias Setting and Sample Rate
Bit 7
Bit 6
Bit 5
∆ mA
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
61
60
59
58
57
56
55
54
53
52
51
–54
−27
−42
−51
−55
27
–56
–58
–60
–62
–64
–66
–68
–70
–72
–74
SNR-00
SNR-01
SNR-10
SNR-11
69
27
THD-00
THD-01
THD-10
THD-11
65.0
62.5
60.0
57.5
55.0
52.5
50.0
47.5
45.0
42.5
–20
–25
–30
–35
–40
–45
–50
–55
–60
–65
SNR_RxPGA = 0dB
20
30
40
50
60
70
80
SAMPLE RATE (MSPS)
SNR_RxPGA = 36dB
THD_RxPGA = 0dB
Figure 82. SNR and THD Performance vs. fADC and SPGA Bias Setting with
RxPGA = 0 dB, fIN = 10 MHz, LPF set to 26 MHz, and AIN = −1 dBFS
The ADC is based on a pipeline architecture with each stage
consisting of a switched capacitor amplifier. Therefore, its per-
formance vs. bias level is mostly dependent on the sample rate.
Figure 83 shows how the typical current consumption seen at
AVDD (Pins 35 and 40) varies as a function of Bits (2:0) and
sample rate, while the remaining bits are maintained at the
default setting of 0. Setting Bit 4 or Register 0x07 corresponds
to the 011 setting, and the settings of 101 and 111 result in
higher current consumption. Figure 84 shows how the SNR and
THD performance are affected for a 10 MHz sine wave input
for the lower power settings as the ADC sample rate is swept
from 20 MHz to 80 MHz.
THD_RxPGA = 36dB
010
40.0
000
–70
100
001
011
CPGA BIAS SETTING-BITS (7:5)
Figure 80. THD vs. fIN Performance and RxPGA Bias Settings
(000,001,010,100 with RxPGA = 0 and +36 dB and AIN = −1 dBFS,
LPF set to 26 MHz, and fADC = 50 MSPS)
The SPGA is implemented as a switched capacitor amplifier%
therefore, its performance vs. bias level is mostly dependent on
the sample rate. Figure 81 shows how the typical current
consumption seen at AVDD (Pin 35 and Pin 40) varies as a
function of Bits (4:3) and sample rate, while the remaining bits
are maintained at the default setting of 0. Figure 82 shows how
the SNR and THD performance is affected for a 10 MHz sine
wave input as the ADC sample rate is swept from 20 MHz to 80
MHz. The SNR and THD performance remains relatively stable,
suggesting that the SPGA bias can often be reduced from its de-
fault setting without impacting the device’s overall performance.
Rev. A | Page 41 of 48
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