AD9865
at OSCIN (or RXCLK) can be determined upon power up. Also,
this clock has near 50ꢀ duty cycle, because it is derived from
the VCO. As a result, CLKOUT1 should be selected before
CLKOUT2 as the primary source for system clock distribution.
Table 22. SPI Registers for CLK Synthesizer
Address (Hex)
Bit
Description
0x04
(4)
ADC CLK from PLL
PLL divide factor (P)
PLL multiplication factor (M)
CLKOUT2 divide number
CLKOUT2 invert
(3:2)
(1:0)
(7:6)
(5)
CLKOUT2 is a divided version of the reference frequency, fOSCIN
and can be set to be a submultiple integer of fOSCIN (fOSCIN/2L,
where L = 0, 1, or 2). With L set to 0, the output of CLKOUT2 is
a delayed version of the signal appearing at OSCIN, exhibiting
the same duty cycle characteristics. With L set to 1 or 2, the
output of CLKOUT2 is a divided version of the OSCIN signal,
exhibiting a near 50ꢀ duty cycle, but without having a determi-
nistic phase relationship relative to CLKOUT1 (or RXCLK).
,
0x06
(4)
CLKOUT2 disable
(3:2)
(1)
CLKOUT1 divide number
CLKOUT1 invert
(0)
CLKOUT1 disable
Rev. A | Page 38 of 48
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