AD9865
POWER CONTROL AND DISSIPATION
POWER-DOWN
HALF-DUPLEX POWER SAVINGS
The AD9865 provides the ability to control the power-on state
of various functional blocks. The state of the PWRDWN pin
along with the contents of Register 0x01 and Register 0x02
allow two user-defined power settings that are pin selectable.
The default settings1 are such that Register 0x01 has all blocks
powered on (all bits 0), while Register 0x02 has all blocks
powered down excluding the PLL such that the clock signal
remains available at CLKOUT1 and CLKOUT2. When the
PWRDWN pin is low, the functional blocks corresponding to
the bits in Register 0x01 are powered down. When the
PWRDWN is high, the functional blocks corresponding to the
bits in Register 0x02 are powered down. PWRDWN
immediately affects the designated functional blocks with
minimum digital delay.
Significant power savings can be realized in applications having
a half-duplex protocol allowing only the Rx or Tx path to be
operational at any instance. The power savings method depends
on whether the AD9865 is configured for a full- or half-duplex
interface. Functional blocks having fast power on/off times for
the Tx and Rx path are controlled by the following bits:
TxDAC/IAMP, TX Digital, ADC, and RxPGA.
In the case of a full-duplex digital interface (MODE = 1), one
can set Register 0x01 to 0x60 and Register 0x02 to Register 0x05
(or vice versa) such that the AD9865’s Tx and Rx path are never
powered on simultaneously. The PWRDWN pin can then be
used to control which path is powered on, depending on the
burst type. During a Tx burst, the Rx path’s PGA and ADC
blocks can typically be powered down within 100 ns, while the
Tx paths DAC, IAMP, and digital filter blocks are powered up
within 0.5 µs. For an Rx burst, the Tx path’s can be powered
down within 100 ns, while the Rx circuitry is powered up
within 2 µs.
Table 23. SPI Registers Associated with Power-Down and
Half-Duplex Power Savings
Address (Hex)
Bit
(7)
(6)
(5)
(4)
(3)
(2)
(1)
(0)
(7)
(6)
(5)
(4)
(3)
(2)
(1)
(0)
(7:3)
(2)
Description
Comments
0x01
PLL
PWRDWN = 0.
TXQUIET
Setting the
pin low allows it to be used with the full-
TxDAC/IAMP
TX Digital
REF
duplex interface to quickly power down the IAMP and disable
the interpolation filter. This is meant to maintain backward
compatibility with the AD9875/AD9876 MxFEs with the excep-
tion that the TxDAC remains powered, if its IOUTP outputs are
used. In most applications, the interpolation filter needs to be
flushed with 0s before or after being powered down. This
ensures that upon power-up, the TxDAC (and IAMP) have a
negligible differential dc offset, thus preventing spectral splatter
due to an impulse transient.
Default setting is all
functional blocks
powered on.
ADC CML
ADC
PGA BIAS
RxPGA
0x02
PLL
PWRDWN = 1.
TxDAC/IAMP
TX Digital
REF
Default setting is all
functional blocks
powered off
Applications using a half-duplex interface (MODE = 0) can
benefit from an additional power savings feature made available
in Register 0x03. This register is effective only for a half-duplex
interface. Besides providing power savings for half-duplex
applications, this feature allows the AD9865 to be used in
applications that need only its Rx (or Tx) path functionality
through pin-strapping, making a serial port interface (SPI)
optional. This feature also allows the PWRDWN pin to retain
its default function as a master power control, as defined in
Table 10.
ADC CML
ADC
excluding PLL.
PGA BIAS
RxPGA
0x03
Tx OFF Delay
Half-duplex power
savings.
Rx PWRDWN
via TXEN
(1)
(0)
Enable Tx
PWRDWN
Enable Rx
PWRDWN
The default settings for Register 0x03 provide fast power control
of the functional blocks in the Tx and Rx signal paths (outlined
above) using the TXEN pin. The TxDAC still remains powered
on in this mode, while the IAMP is powered down. Significant
current savings are typically realized when the IAMP is
powered down.
1 With MODE = 1 and CONFIG =1, Reg. 0x02 default settings are with all blocks
powered off, with RXCLK providing a buffered version of the signal
appearing at OSCIN. This setting results in the lowest power consumption
upon power-up, while still allowing AD9865 to generate the system clock via
a crystal.
For a Tx burst, the falling edge of TXEN is used to generate an
internal delayed signal for powering down the Tx circuitry.
Upon receipt of this signal, power-down of the Tx circuitry
Rev. A | Page 39 of 48
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