AD9865
PCB DESIGN CONSIDERATIONS
may be allocated to the IAMP, if its supply voltage differs from
the 3.3 V required by AVDD and CLKVDD. On the digital side,
DVDD and DRVDD can share the same 3.3 V digital power
plane. This digital power plane brings the current used to power
the digital portion of the MxFE and its output drivers. This
digital plane should be kept from going underneath the analog
components.
Although the AD9865 is a mixed-signal device, the part should
be treated as an analog component. The on-chip digital circuitry
has been specially designed to minimize the impact of its digital
switching noise on the MxFE’s analog performance.
To achieve the best performance, the power, grounding, and
layout recommendations in this section should be followed.
Assembly instructions for the micro-lead frame package can be
found in an application note from Amkor at:
http://www.amkor.com/products/notes_papers/MLF_AppNote
_0902.pdf.
The analog and digital power planes allocated to the MxFE may
be fed from the same low noise voltage source% however, they
should be decoupled from each other to prevent the noise
generated in the digital portion of the MxFE from corrupting
the AVDD supply. This can be done by using ferrite beads be-
tween the voltage source and the respective analog and digital
power planes with a low ESR, bulk decoupling capacitor on the
MxFE side of the ferrite. Each of the MxFE’s supply pins
(AVDD, CLKVDD, DVDD, and DRVDD) should also have
dedicated low ESR, ESL decoupling capacitors. The decoupling
capacitors should be placed as close to the MxFE supply pins as
possible.
COMPONENT PLACEMENT
If the three following guidelines of component placement are
followed, chances for getting the best performance from the
MxFE are greatly increased. First, manage the path of return
currents flowing in the ground plane so that high frequency
switching currents from the digital circuits do not flow on the
ground plane under the MxFE or analog circuits. Second, keep
noisy digital signal paths and sensitive receive signal paths as
short as possible. Third, keep digital (noise generating) and
analog (noise susceptible) circuits as far away from each other
as possible.
GROUND PLANES
The AD9865 evaluation board uses a single serrated ground
plane to help prevent any high frequency digital ground
currents from coupling over to the analog portion of the ground
plane. The digital currents affiliated with the high speed data
bus interface (Pin 1 to Pin 16) have the highest potential of
generating problematic high frequency noise. A ground
serration that contains these currents should reduce the effects
of this potential noise source.
To best manage the return currents, pure digital circuits that
generate high switching currents should be closest to the power
supply entry. This keeps the highest frequency return current
paths short and prevents them from traveling over the sensitive
MxFE and analog portions of the ground plane. Also, these
circuits should be generously bypassed at each device, which
further reduces the high frequency ground currents. The MxFE
should be placed adjacent to the digital circuits, such that the
ground return currents from the digital sections do not flow in
the ground plane under the MxFE.
The ground plane directly underneath the MxFE should be
continuous and uniform. The 64-lead LFCSP package is
designed to provide excellent thermal conductivity. This is
partly achieved by incorporating an exposed die paddle on the
bottom surface of the package. However, to take full advantage
of this feature, the PCB must have features to effectively
conduct heat away from the package. This can be achieved by
incorporating thermal pad and thermal vias on the PCB. While
a thermal pad provides a solderable surface on the top surface
of the PCB (to solder the package die paddle on the board),
thermal vias are needed to provide a thermal path to inner
and/or bottom layers of the PCB to remove the heat.
The AD9865 has several pins that are used to decouple sensitive
internal nodes. These pins are REFIO, REFB, and REFT. The
decoupling capacitors connected to these points should have
low ESR and ESL. These capacitors should be placed as close to
the MxFE as possible (see Figure 75) and be connected directly
to the analog ground plane. The resistor connected to the
REFADJ pin should also be placed close to the device and
connected directly to the analog ground plane.
POWER PLANES AND DECOUPLING
Lastly, all ground connections should be made as short as
possible. This results in the lowest impedance return paths and
the quietest ground connections.
While the AD9865 evaluation board demonstrates a very good
power supply distribution and decoupling strategy, it can be
further simplified for many applications. The board has four
layers: two signal layers, one ground plane, and one power
plane. While the power plane on the evaluation board is split
into multiple analog and digital subsections, a permissible
alternative would be to have AVDD and CLKVDD share the
same analog 3.3 V power plane. A separate analog plane/supply
SIGNAL ROUTING
The digital Rx and Tx signal paths should be kept as short as
possible. Also, the impedance of these traces should have a
controlled characteristic impedance of about 50 Ω. This
prevents poor signal integrity and the high currents that can
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