AD9807/AD9805
ANALOG
INPUTS
R0, G0, B0
R1, G1, B1
Rn, Gn, Bn
tAD
tAD
STRTLN
tC1C2A
tCRA
tH
tS
tC2C1A
tC1A
CDSCLK1
tC2A
tC1AD
CDSCLK2
ADCCLK
tSTL1
tACLK
tACLK
R
G
tCP2
B
R
G
B
R
G
B
tGOH
tGOS
GAIN<n:0>
OFFSET<m:0>
R0
G0
B0
R1
G1
B1
Figure 1a. 3-Channel CDS-Mode Clock Tim ing
ANALOG
INPUTS
R0, G0, B0
R1, G1, B1
Rn, Gn, Bn
(0V)
tAD
STRTLN
CDSCLK1
ADCCLK
tCRA
tH
tS
tC2A
tACLK
tSTL1
tACLK
tCP
tGOS
tGOH
GAIN<n:0>
OFFSET<m:0>
Figure 1b. 3-Channel SHA-Mode Clock Tim ing
ANALOG
INPUTS
PIXEL 0
PIXEL 1
PIXEL n
tAD
tAD
STRTLN
tC1B
tCRB
tC1C2B
tS
tH
tC2C1B
CDSCLK1
tC2B
CDSCLK2
ADCCLK
tACLK
tACLK
tSTL2
tGOS
tGOH
tCP
GAIN<n:0>
OFFSET<m:0>
G2
G0
G1
Figure 1c. 1-Channel CDS-Mode Clock Tim ing (for B and G Only)
REV. 0
–8–
ADI [ ADI ]
