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AD9807JS 参数 Datasheet PDF下载

AD9807JS图片预览
型号: AD9807JS
PDF下载: 下载PDF文件 查看货源
内容描述: 完整的12位/ 10位6 MSPS CCD / CIS信号处理器 [Complete 12-Bit/10-Bit 6 MSPS CCD/CIS Signal Processors]
分类和应用: 微控制器和处理器外围集成电路uCs集成电路uPs集成电路
文件页数/大小: 24 页 / 242 K
品牌: AD [ ANALOG DEVICES ]
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AD9807/AD9805
PIN CONFIGURATION
GAIN<11>
GAIN<10>
GAIN<9>
GAIN<8>
GAIN<7>
GAIN<6>
GAIN<5>
GAIN<4>
GAIN<3>
GAIN<2>
GAIN<1>
GAIN<0>
DVDD
A2
A1
A0
DOUT<11>
46
DOUT<10>
48
47
45
44
43
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
AVDD
1
AVSS
2
CAPT
3
CAPT
4
CAPB
5
CAPB
6
VREF
7
CML
8
VINR
9
AVSS
10
VING
11
AVSS
12
VINB
13
AVSS
14
AVDD
15
STRTLN
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PIN 1
IDENTIFIER
DVSS
DOUT<9>
DOUT<8>
DOUT<7>/MPU<7>
DOUT<6>/MPU<6>
DRVDD
AD9807
TOP VIEW
(Not to Scale)
42
41
40
39
DRVSS
DOUT<5>/MPU<5>
38
DOUT<4>/MPU<4>
37
36
35
34
DOUT<3>/MPU<3>
DOUT<2>/MPU<2>
DOUT<1>/MPU<1>
DOUT<0>/MPU<0>
33
OEB
OFFSET<5>
OFFSET<4>
OFFSET<3>
OFFSET<2>
ADCCLK
OFFSET<7>
OFFSET<6>
OFFSET<1>
OFFSET<0>
CDSCLK1
CDSCLK2
DVSS
DVDD
CSB
RDB
PIN DESCRIPTIONS
Pin No.
1, 15
2, 10, 12, 14
3, 4
5, 6
7
8
9
11
13
16
17
18
19
28, 52
29, 51
20
21–26
27
30
31
32
33
34
35–39, 42
40
41
43
44–46
47
48, 49, 50
53
54–63
64
REV. 0
Pin Name
AVDD
AVSS
CAPT
CAPB
VREF
CML
VINR
VING
VINB
STRTLN
CDSCLK1
CDSCLK2
ADCCLK
DVSS
DVDD
OFFSET<7>
OFFSET<6:1>
OFFSET<0>
CSB
RDB
WRB
OEB
DOUT<0>/MPU<0>
DOUT<1:6>/MPU<1:6>
DRVSS
DRVDD
DOUT<7>/MPU<7>
DOUT<8:10>
DOUT<11>
A0, A1, A2
GAIN<0>
GAIN<1:10>
GAIN<11>
Type
P
P
AO
AO
AO
AO
AI
AI
AI
DI
DI
DI
DI
P
P
DI
DI
DI
DI
DI
DI
DI
DIO
DIO
P
P
DIO
DO
DO
DI
DI
DI
DI
–5–
Description
+5 V Analog Supply.
Analog Ground.
Reference Decoupling. See Figure 22.
Reference Decoupling.
Internal Reference Output. Decouple with 10
µF
+ 0.1
µF.
Internal Bias Voltage. Decouple with 0.1
µF.
Analog Input, Red.
Analog Input, Green.
Analog Input, Blue.
STRTLN. Indicates beginning of scan line.
CDS Reset Clock Pulse Input.
CDS Data Clock Pulse Input.
A/D Sample Clock Input.
Digital Ground.
+5 V Digital Supply.
Pixel Rate Offset Coefficient Inputs. Most Significant Bit.
Pixel Rate Offset Coefficient Inputs.
Pixel Rate Offset Coefficient Inputs. Least Significant Bit.
Chip Select. Active Low.
Read Strobe. Active Low.
Write Strobe. Active Low.
Output Enable. Active Low.
Data Output LSB/Register Input LSB
Data Outputs/Register Inputs.
Digital Driver Ground
Digital Driver Supply
Data Output/Register Input MSB.
Data Outputs.
Data Output MSB.
Register Select Pins.
Pixel Rate Gain Coefficient Input. LSB.
Pixel Rate Gain Coefficient Inputs.
Pixel Rate Gain Coefficient Input. MSB.
TYPE: AI = Analog Input; AO = Analog Output; DI = Digital Input; DO = Digital Output; DIO = Digital Input/Output; P = Power.
WRB