AD9807/AD9805
TIMING SPECIFICATIONS
(T
Parameter
MIN
to T
MAX
with AV
DD
= +5.0 V, DV
DD
= +5.0 V, unless otherwise noted)
Symbol
t
CRA
t
CRB
t
C1A
t
C1B
t
C2A
t
C2B
t
Q
t
C2C1A
t
C2C1B
t
C1C2A
t
C1C2B
t
C1AD
t
ACLK
t
CP
t
CP2
t
STL1
t
STL2
t
GOS
t
GOH
t
S
t
H
t
AD
t
AS
t
AH
t
DS
t
DH
t
CSS
t
CSH
t
PWW
t
PWR
t
DD
t
OD
t
EDV
t
HZ
Min
500
166
30
30
30
30
20
80
40
20
20
35
50
166
200
60
30
15
15
15
15
10
15
15
15
15
15
15
25
50
40
15
15
5
6
Table I. Output Controls
Typ
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ADCCLK Cycles
CLOCK PARAMETERS
3-Channel Conversion Rate
1-Channel Conversion Rate
CDSCK1 Pulse Width
CDSCK1 Pulse Width
CDSCK2 Pulse Width
CDSCK2 Pulse Width
CDS Clocks Digital Quiet Time
CDSCK2 Falling to CDSCK1 Rising
CDSCK2 Falling to CDSCK1 Rising
CDSCK1 Falling to CDSCK2 Rising
CDSCK1 Falling to CDSCK2 Rising
ADCCLK Rising to CDSCK1 Falling
ADCCLK Pulse Width
ADCCLK Period
ADCCLK Period (Red Single Channel Mode)
3-Channel Settling Time
1-Channel Settling Time (B and G Only)
ADCCLK Rising to Control Data Setup
ADCCLK Rising to Control Data Hold
STRTLN Rising, Falling Setup
STRTLN Rising, Falling Hold
Aperture Delay
REGISTER WRITE/READ
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
Chip Select Setup Time
Chip Select Hold Time
Write Pulse Width
Read Pulse Width
Read To Data Valid
DATA OUTPUT
Output Delay
3-State to Data Valid
Output Enable High to 3-State
Latency
CSB
RDB
WRB
OEB
DOUT
0
0
0
x
X
0
0
1
x
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
Z
1
x
x
0
1
x
x
1
Q
X
MPU
D
X
MPU
Q
Z
ADC
LEGEND:
x = Don't Care
X = Unknown (Not Recommended)
Q = Outputs
D = Inputs
Z = 3-State
–4–
REV. 0
AD [ ANALOG DEVICES ]
