AD9807/AD9805
TIMING SPECIFICATIONS
P aram eter
(TMIN to TMAX with AV = +5.0 V, DV = +5.0 V, unless otherwise noted)
DD
DD
Sym bol
Min
Typ
Max
Units
CLOCK PARAMET ERS
3-Channel Conversion Rate
1-Channel Conversion Rate
CDSCK1 Pulse Width
CDSCK1 Pulse Width
CDSCK2 Pulse Width
tCRA
tCRB
tC1A
tC1B
tC2A
tC2B
tQ
tC2C1A
tC2C1B
tC1C2A
tC1C2B
tC1AD
tACLK
tCP
500
166
30
30
30
30
20
80
40
20
20
35
50
166
200
60
30
15
15
15
15
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CDSCK2 Pulse Width
CDS Clocks Digital Quiet T ime
CDSCK2 Falling to CDSCK1 Rising
CDSCK2 Falling to CDSCK1 Rising
CDSCK1 Falling to CDSCK2 Rising
CDSCK1 Falling to CDSCK2 Rising
ADCCLK Rising to CDSCK1 Falling
ADCCLK Pulse Width
ADCCLK Period
ADCCLK Period (Red Single Channel Mode)
3-Channel Settling T ime
1-Channel Settling T ime (B and G Only)
ADCCLK Rising to Control Data Setup
ADCCLK Rising to Control Data Hold
ST RT LN Rising, Falling Setup
ST RT LN Rising, Falling Hold
Aperture Delay
tCP2
tST L1
tST L2
tGOS
tGOH
tS
tH
tAD
REGIST ER WRIT E/READ
Address Setup T ime
Address Hold T ime
Data Setup T ime
tAS
tAH
tDS
tDH
tCSS
tCSH
tPWW
tPWR
tDD
15
15
15
15
15
15
25
50
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Hold T ime
Chip Select Setup T ime
Chip Select Hold T ime
Write Pulse Width
Read Pulse Width
Read T o Data Valid
DAT A OUT PUT
Output Delay
3-State to Data Valid
Output Enable High to 3-State
Latency
tOD
tEDV
tHZ
15
6
ns
ns
ns
15
5
ADCCLK Cycles
Table I. O utput Controls
CSB
RD B
WRB
O EB
0
0
0
x
0
0
1
x
0
1
0
0
0
1
0
1
0
1
1
0
0
1
x
x
0
1
x
x
1
1
1
1
D O UT
X
Q
X
D
X
Z
Q
Z
MPU
MPU
ADC
LEGEND:
x
= Don't Care
X = Unknown (Not Recommended)
Q = Outputs
D = Inputs
Z = 3-State
REV. 0
–4–
ADI [ ADI ]
