AD9650
TIMING SPECIFICATIONS
Table 5.
Parameter
SYNC TIMING REQUIREMENTS
t
SSYNC
t
HSYNC
SPI TIMING REQUIREMENTS
t
DS
t
DH
t
CLK
t
S
t
H
t
HIGH
t
LOW
t
EN_SDIO
t
DIS_SDIO
1
Conditions
SYNC to rising edge of CLK+ setup time
SYNC to rising edge of CLK+ hold time
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
SCLK pulse width high
SCLK pulse width low
Time required for the SDIO pin to switch from an input to an output relative to the
SCLK falling edge
Time required for the SDIO pin to switch from an output to an input relative to the
SCLK rising edge
Limit
0.3
0.40
2
2
40
2
2
10
10
10
10
Unit
ns typ
ns typ
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
See Figure 93.
Timing Diagrams
N–1
N
V
IN
N+1
N+2
t
A
N+3
N+4
N+5
t
CH
CLK+
CLK–
t
CLK
t
DCO
DCOA/DCOB
t
SKEW
08919-002
08919-003
CH A/CH B DATA
N – 13
N – 12
N – 11
N – 10
N–9
N–8
t
PD
Figure 2. CMOS Default Output Mode Data Output Timing
N–1
N
V
IN
t
A
N+3
N+1
N+2
N+4
N+5
t
CH
CLK+
CLK–
t
CLK
t
DCO
DCOA/DCOB
t
SKEW
t
PD
CH A/CH B DATA
CH A CH B CH A
CH B CH A CH B
N – 12 N – 12 N – 11 N – 11 N – 10 N – 10
CH A
N–9
CH B
N–9
CH A
N–8
Figure 3. CMOS Interleaved Output Mode Data Output Timing
Rev. 0 | Page 8 of 44
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