AD9650
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, V
IN
= −1.0 dBFS differential input, 1.35 V internal reference, and DCS enabled,
unless otherwise noted.
Table 4.
Parameter
CLOCK INPUT PARAMETERS
Input Clock Rate
Conversion Rate
DCS Enabled
DCS Disabled
CLK Period—Divide-by-1
Mode (t
CLK
)
CLK Pulse Width High (t
CH
)
Divide-by-1 Mode, DCS
Enabled
Divide-by-1 Mode, DCS
Disabled
Divide-by-2 Mode
Through Divide-by-8
Mode
Aperture Delay (t
A
)
Aperture Uncertainty
(Jitter, t
J
)
DATA OUTPUT PARAMETERS
CMOS Mode
Data Propagation Delay
(t
PD
)
DCO Propagation Delay
(t
DCO
DCO to Data Skew (t
SKEW
)
LVDS Mode
Data Propagation Delay
(t
PD
)
DCO Propagation Delay
(t
DCO
DCO to Data Skew (t
SKEW
)
CMOS Mode Pipeline Delay
(Latency)
LVDS Mode Pipeline Delay
(Latency) Channel A/
Channel B
Wake-Up Time
Out-of-Range Recovery
Time
1
2
Temp
Full
Full
Full
Full
AD9650BCPZ-25
Min
Typ
Max
200
20
10
40
25
25
AD9650BCPZ-65
Min
Typ
Max
520
20
10
15.4
65
65
AD9650BCPZ-80
Min Typ
Max
640
20
10
12.5
80
80
AD9650BCPZ-105
Min Typ
Max
640
20
10
9.5
105
105
Unit
MHz
MSPS
MSPS
ns
Full
Full
Full
12
19
0.8
20
20
28
21
4.65
7.33
0.8
7.70
7.70
10.75
8.07
3.75
5.95
0.8
6.25
6.25
8.75
6.55
2.85
4.5
0.8
4.75
4.75
6.65
5.0
ns
ns
ns
Full
Full
1.0
0.100
1.0
0.090
1.0
0.080
1.0
0.075
ns
ps rms
Full
Full
Full
Full
Full
Full
Full
Full
2.8
3.5
3.1
4.2
2.8
3.5
3.1
4.2
2.8
3.5
3.1
4.2
2.8
3.5
3.1
4.2
ns
ns
−0.6
2.9
−0.4
3.7
3.9
0
4.5
−0.6
2.9
−0.4
3.7
3.9
0
4.5
−0.6
2.9
−0.4
3.7
3.9
0
4.5
−0.6
2.9
−0.4
3.7
3.9
0
4.5
ns
ns
ns
−0.1
+0.2
12
12/12.5
+0.5
−0.1
+0.2
12
12/12.5
+0.5
−0.1
+0.2
12
12/12.5
+0.5
−0.1
+0.2
12
12/12.5
+0.5
ns
Cycles
Cycles
Full
Full
500
2
500
2
500
2
500
2
μs
Cycles
Conversion rate is the clock rate after the divider.
Additional DCO delay can be added by writing to Bit 0 through Bit 4 in SPI Register 0x17 (see Table 17).
3
Wake-up time is defined as the time required to return to normal operation from power-down mode.
Rev. 0 | Page 7 of 44
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