AD9650
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, V
IN
= −1.0 dBFS differential input, 1.35 V internal reference, and DCS enabled, unless
otherwise noted.
Table 3.
Parameter
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
Input Common-Mode Range
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
SYNC INPUT
Logic Compliance
Internal Bias
Input Voltage Range
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
LOGIC INPUT (CSB)
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUT (SCLK/DFS)
High Level Input Voltage
Low Level Input Voltage
High Level Input Current (V
IN
= 1.8 V)
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUT/OUTPUT (SDIO/DCS)
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUTS (OEB, PDWN)
High Level Input Voltage
Low Level Input Voltage
High Level Input Current (V
IN
= 1.8 V)
Low Level Input Current
Input Resistance
Input Capacitance
Temperature
Min
Typ
CMOS/LVDS/LVPECL
0.9
0.3
AGND
0.9
−100
−100
8
9
10
CMOS
0.9
AGND
1.2
AGND
−100
−100
12
1.22
0
−10
40
26
2
1.22
0
−92
−10
26
2
1.22
0
−10
38
26
5
1.22
0
−90
−10
26
5
2.1
0.6
−134
+10
2.1
0.6
+10
128
2.1
0.6
−135
+10
1
16
AVDD
AVDD
0.6
+100
+100
20
2.1
0.6
+10
132
3.6
AVDD
1.4
+100
+100
12
Max
Unit
Full
Full
Full
Full
Full
Full
Full
Full
V
V p-p
V
V
μA
μA
pF
kΩ
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
V
V
V
V
μA
μA
pF
kΩ
V
V
μA
μA
kΩ
pF
V
V
μA
μA
kΩ
pF
V
V
μA
μA
kΩ
pF
V
V
μA
μA
kΩ
pF
Rev. 0 | Page 5 of 44
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