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AD9650BCPZ-65 参数 Datasheet PDF下载

AD9650BCPZ-65图片预览
型号: AD9650BCPZ-65
PDF下载: 下载PDF文件 查看货源
内容描述: 16位, 25 MSPS / 65 MSPS / 80 MSPS / 105 MSPS , 1.8 V双通道模拟数字转换器( ADC ) [16-Bit, 25 MSPS/65 MSPS/80 MSPS/105 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC)]
分类和应用: 转换器模数转换器
文件页数/大小: 44 页 / 1640 K
品牌: AD [ ANALOG DEVICES ]
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AD9650
ADC AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, V
IN
= −1.0 dBFS differential input, 1.35 V internal reference, DCS disabled,
unless otherwise noted.
Table 2.
Parameter
SIGNAL-TO-NOISE RATIO (SNR)
f
IN
= 9.7 MHz
f
IN
= 30 MHz
f
IN
= 70 MHz
f
IN
= 141 MHz
SIGNAL-TO-NOISE-AND-DISTORTION
(SINAD)
f
IN
= 9.7 MHz
f
IN
= 30 MHz
f
IN
= 70 MHz
f
IN
= 141 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
f
IN
= 9.7 MHz
f
IN
= 30 MHz
f
IN
= 70 MHz
f
IN
= 141 MHz
WORST SECOND OR THIRD HARMONIC
f
IN
=9.7 MHz
f
IN
= 30 MHz
f
IN
= 70 MHz
f
IN
= 141 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
f
IN
= 9.7 MHz
f
IN
= 30 MHz
f
IN
= 70 MHz
f
IN
= 141 MHz
WORST OTHER (HARMONIC OR SPUR)
f
IN
= 9.7 MHz
f
IN
= 30 MHz
f
IN
= 70 MHz
f
IN
= 141 MHz
TWO-TONE SFDR
f
IN
= 7.2 MHz (−7 dBFS ), 8.4 MHz
(−7 dBFS)
f
IN
= 25 MHz (−7 dBFS ), 30 MHz
(−7 dBFS)
f
IN
= 125 MHz (−7 dBFS ), 128 MHz
(−7 dBFS)
CROSSTALK
ANALOG INPUT BANDWIDTH
1
2
Temp
25°C
25°C
Full
25°C
25°C
AD9650BCPZ-25
Min
Typ
Max
83
81.5
81.8
79.5
AD9650BCPZ-65
Min Typ
Max
83
82
81.5
81
79.5
AD9650BCPZ-80
Min Typ
Max
83
82
81.6
81
80
AD9650BCPZ-105
Min Typ
Max
82.5
82
80.5
80
80
Unit
dBFS
dBFS
dBFS
dBFS
dBFS
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
Full
25°C
82.2
80
81.5
78
81
82
81.2
80.7
79.2
75
13.5
13.2
13.0
12.9
−94
−93
−91.5
−88
−86
−79
94
93
88
87
86
79
−105
−105
−97
−97
−97
−97
82
82
80
78.5
75.1
13.5
13.2
13.0
13.0
−95.5
−92
−87
−86
−79
95.5
92
87
86
79
−105
−105
−97
−97
−97
82
80.4
78.8
75.5
13.3
13.2
13.0
12.3
−91
−90
−87
−92
−80
91
90
92
80
−100
−101
−94
−97
−88
dBFS
dBFS
dBFS
dBFS
dBFS
Bits
Bits
Bits
Bits
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
13.5
13.0
12.7
−95
−85
−87
95
85
91.5
87
−110
−102
−97
87
84
90
83
−105
500
−105
500
87
83
−105
500
87
84
−105
500
dBc
dBc
dBFS
MHz
See the
Application Note,
Understanding High Speed ADC Testing and Evaluation,
for a complete set of definitions.
Measurements made with a divide-by-4 clock rate to minimize the effects of clock jitter on the SNR performance.
3
Crosstalk is measured with a 170 MHz tone at −1 dBFS on one channel and no input on the alternate channel.
Rev. 0 | Page 4 of 44