AD9650
Pin No.
Mnemonic
D7A
Type
Description
33
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data (MSB).
Channel A Overrange Output.
Channel B CMOS Output Data (LSB).
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data (MSB).
Channel B Overrange Output
Channel A Data Clock Output.
Channel B Data Clock Output.
34
35
36
38
39
40
41
42
43
4
5
6
7
8
9
11
12
13
14
15
16
17
18
20
21
22
24
23
D8A
D9A
D10A
D11A
D12A
D13A
D14A
D15A
ORA
D0B
D1B
D2B
D3B
D4B
D5B
D6B
D7B
D8B
D9B
D10B
D11B
D12B
D13B
D14B
D15B
ORB
DCOA
DCOB
SPI Control
45
44
46
SCLK/DFS
SDIO/DCS
CSB
Input
SPI Serial Clock/Data Format Select Pin in External Pin Mode.
Input/output SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode.
Input
SPI Chip Select (Active Low).
ADC Configuration
47
48
OEB
PDWN
Input
Input
Output Enable Input (Active Low) in External Pin Mode.
Power-Down Input in External Pin Mode. In SPI mode, this input can be
configured as power-down or standby.
Rev. 0 | Page 12 of 44
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