AD9650
SPECIFICATIONS
ADC DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, V
IN
= −1.0 dBFS differential input, 1.35 V internal reference, DCS disabled,
unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
MATCHING CHARACTERISTIC
Offset Error
Gain Error
TEMPERATURE DRIFT
Offset Error
Gain Error
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1.35 V
Mode)
Load Regulation at 1.0 mA
INPUT REFERRED NOISE
VREF = 1.35 V
ANALOG INPUT
Input Span, VREF = 1.35 V
Input Capacitance
Input Common-Mode Voltage
REFERENCE INPUT RESISTANCE
POWER SUPPLIES
Supply Voltage
AVDD
DRVDD
Supply Current
IAVDD
IDRVDD
(1.8 V CMOS)
IDRVDD
(1.8 V LVDS)
POWER CONSUMPTION
DC Input
Sine Wave Input
(DRVDD =
1.8 V CMOS Output Mode)
Sine Wave Input
(DRVDD =
1.8 V LVDS Output Mode)
Standby Power
Power-Down Power
1
2
Temp
Full
Full
Full
Full
Full
25°C
Full
25°C
Full
Full
Full
Full
Full
Full
25°C
AD9650BCPZ-25
Min Typ
Max
16
Guaranteed
±0.2
±0.5
±0.4
±2.5
−1
+1.3
±0.7
±3
±1.6
±0.1
±0.5
±2
±15
±7
10
1.5
±14
±0.4
±1.3
AD9650BCPZ-65
Min Typ
Max
16
Guaranteed
±0.2
±0.5
±0.4
±2.5
−1
+1.3
±0.7
±5
±2.5
±0.1
±0.5
±2
±15
±7
10
1.5
±14
±0.4
±1.3
AD9650BCPZ-80
Min Typ
Max
16
Guaranteed
±0.4
±0.70
±0.4
±2.5
+1.3
±0.7
±6
±2.5
±0.1
±0.5
±2
±15
±7
10
1.5
±14
±0.4
±1.3
AD9650BCPZ-105
Min Typ
Max
16
Guaranteed
±0.4
±0.7
±0.4
±2.5
−1
+1.3
±0.7
±6
±3
±0.1
±0.5
±2
±15
±7
10
1.5
±14
±0.4
±1.3
Unit
Bits
−1
% FSR
% FSR
LSB
LSB
LSB
LSB
% FSR
% FSR
ppm/°C
ppm/°C
mV
mV
LSB
rms
V p-p
pF
V
kΩ
Full
Full
Full
Full
2.7
11
0.9
6
2.7
11
0.9
6
2.7
11
0.9
6
2.7
11
0.9
6
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
1.7
1.7
1.8
1.8
125
8
72
237
240
355
50
0.25
1.9
1.9
131
1.7
1.7
1.8
1.8
202
23
86
1.9
1.9
209
1.7
1.7
1.8
1.8
267
29
90
1.9
1.9
275
1.7
1.7
1.8
1.8
332
36
100
1.9
1.9
340
V
V
mA
mA
mA
254
397
405
520
50
0.25
408
522
533
642
50
0.25
537
656
663
778
50
0.25
675
mW
mW
mW
mW
mW
2.5
2.5
2.5
2.5
Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.
Input capacitance refers to the effective capacitance between one differential input pin and AGND.
3
Standby power is measured with a dc input and with the CLK+ and CLK− pins inactive (set to AVDD or AGND).
Rev. 0 | Page 3 of 44
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