16-Bit, 25 MSPS/65 MSPS/80 MSPS/105 MSPS,
1.8 V Dual Analog-to-Digital Converter (ADC)
AD9650
FEATURES
1.8 V analog supply operation
1.8 V CMOS or LVDS output supply
SNR
82 dBFS at 30 MHz input and 105 MSPS data rate
83 dBFS at 9.7 MHz input and 25 MSPS data rate
SFDR
90 dBc at 30 MHz input and 105 MSPS data rate
95 dBc at 9.7 MHz input and 25 MSPS data rate
Low power
328 mW per channel at 105 MSPS
119 mW per channel at 25 MSPS
Integer 1-to-8 input clock divider
IF sampling frequencies to 300 MHz
Analog input range of 2.7 V p-p
Optional on-chip dither
Integrated ADC sample-and-hold inputs
Differential analog inputs with 500 MHz bandwidth
ADC clock duty cycle stabilizer
FUNCTIONAL BLOCK DIAGRAM
AVDD
SDIO/ SCLK/
DCS
DFS
SPI
CSB
DRVDD
AD9650
PROGRAMMING DATA
VIN+A
VIN–A
ADC
16
CMOS/LVDS
OUTPUT BUFFER
ORA
D15A (MSB)
TO
D0A (LSB)
CLK+
CLK–
VREF
SENSE
REF
SELECT
DIVIDE 1
TO 8
DUTY CYCLE
STABILIZER
DCO
GENERATION
DCOA
DCOB
ORB
VCM
RBIAS
VIN–B
VIN+B
ADC
MULTICHIP
SYNC
16
CMOS/LVDS
OUTPUT BUFFER
D15B (MSB)
TO
D0B (LSB)
APPLICATIONS
Industrial instrumentation
X-Ray, MRI, and ultrasound equipment
High speed pulse acquisition
Chemical and spectrum analysis
Direct conversion receivers
Multimode digital receivers
Smart antenna systems
General-purpose software radios
Figure 1.
Flexible power-down options allow significant power savings,
when desired.
Programming for setup and control is accomplished using a 3-wire
SPI-compatible serial interface.
The AD9650 is available in a 64-lead LFCSP and is specified over
the industrial temperature range of −40°C to +85°C.
GENERAL DESCRIPTION
The AD9650 is a dual, 16-bit, 25 MSPS/65 MSPS/80 MSPS/
105 MSPS analog-to-digital converter (ADC) designed for
digitizing high frequency, wide dynamic range signals with
input frequencies of up to 300 MHz.
The dual ADC core features a multistage, differential pipelined
architecture with integrated output error correction logic. Each
ADC features wide bandwidth, differential sample-and-hold
analog input amplifiers, and shared integrated voltage reference,
which eases design considerations. A duty cycle stabilizer is
provided to compensate for variations in the ADC clock duty
cycle, allowing the converters to maintain excellent performance.
The ADC output data can be routed directly to the two external
16-bit output ports or multiplexed on a single 16-bit bus. These
outputs can be set to either 1.8 V CMOS or LVDS.
PRODUCT HIGHLIGHTS
1.
2.
3.
On-chip dither option for improved SFDR performance
with low power analog input.
Proprietary differential input that maintains excellent SNR
performance for input frequencies up to 300 MHz.
Operation from a single 1.8 V supply and a separate digital
output driver supply accommodating 1.8 V CMOS or
LVDS outputs.
Standard serial port interface (SPI) that supports various
product features and functions, such as data formatting
(offset binary, twos complement, or gray coding), enabling
the clock DCS, power-down, and test modes.
Pin compatible with the AD9268 and other dual families,
AD9269, AD9251, AD9231, and AD9204. This allows a
simple migration across resolutions and bandwidth.
4.
5.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.
08919-001
AGND
SYNC
PDWN
OEB
NOTES
1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY;
SEE FIGURE 7 FOR LVDS PIN NAMES.
AD [ ANALOG DEVICES ]
