AD7715–SPECIFICATIONS
A
(AVDD = +3 V to +5 V, DVDD = +3 V to +5 V, REF IN(+) = +1.25 V (AD7715-3) or +2.5 V
(AD7715-5); REF IN(–) = AGND; MCLK IN = 1 MHz to 2.4576 MHz unless otherwise noted. All specifications TMIN to TMAX unless otherwise noted.)
Parameter
A Version
Unit
Conditions/Comments
SYSTEM CALIBRATION
Positive Full-Scale Calibration Limit14
(1.05 × VREF)/GAIN
V max
GAIN Is the Selected PGA Gain (1, 2, 32 or 128)
GAIN Is the Selected PGA Gain (1, 2, 32 or 128)
GAIN Is the Selected PGA Gain (1, 2, 32 or 128)
GAIN Is the Selected PGA Gain (1, 2, 32 or 128)
GAIN Is the Selected PGA Gain (1, 2, 32 or 128)
Negative Full-Scale Calibration Limit14 –(1.05 × VREF)/GAIN V max
Offset Calibration Limit15
Input Span15
–(1.05 × VREF)/GAIN V max
0.8 × VREF/GAIN
(2.1 × VREF)/GAIN
V min
V max
POWER REQUIREMENTS
Power Supply Voltages
AVDD Voltage (AD7715-3)
AVDD Voltage (AD7715-5)
DVDD Voltage
+3 to +3.6
+4.75 to +5.25
+3 to +5.25
V
V
V
For Specified Performance
For Specified Performance
For Specified Performance
Power Supply Currents
AVDD Current
AVDD = 3.3 V or 5 V. Gain = 1 to 128 (fCLK IN = 1 MHz) or
Gain = 1 or 2 (fCLK IN = 2.4576 MHz)
0.27
0.6
mA max
mA max
Typically 0.2 mA. BUF Bit of Setup Register = 0
Typically 0.4 mA. BUF Bit of Setup Register = 1
AVDD = 3.3 V or 5 V. Gain = 32 or 128 (fCLK IN = 2.4576 MHz)16
Typically 0.3 mA. BUF Bit of Setup Register = 0
Typically 0.8 mA. BUF Bit of Setup Register = 1
Digital I/Ps = 0 V or DVDD. External MCLK IN
Typically 0.15 mA. DVDD = 3.3 V. fCLK IN = 1 MHz
Typically 0.3 mA. DVDD = 5 V. fCLK IN = 1 MHz
Typically 0.4 mA. DVDD = 3.3 V. fCLK IN = 2.4576 MHz
Typically 0.6 mA. DVDD = 5 V. fCLK IN = 2.4576 MHz
0.5
1.1
mA max
mA max
DVDD Current17
0.18
0.4
0.5
0.8
mA max
mA max
mA max
mA max
dB typ
Power Supply Rejection 18
See Note 19
Normal-Mode Power Dissipation17
AVDD = DVDD = +3.3 V. Digital I/Ps = 0 V or DVDD. External MCLK IN
1.5
2.65
3.3
5.3
mW max BUF Bit = 0. All Gains 1 MHz Clock
mW max BUF Bit = 1. All Gains 1 MHz Clock
mW max BUF Bit = 0. Gain = 32 or 128 @ fCLK IN = 2.4576 MHz
mW max BUF Bit = 1. Gain = 32 or 128 @ fCLK IN = 2.4576 MHz
AVDD = DVDD = +5 V. Digital I/Ps = 0 V or DVDD. External MCLK IN
mW max BUF Bit = 0. All Gains 1 MHz Clock
Normal-Mode Power Dissipation17
3.25
5
mW max BUF Bit = 1. All Gains 1 MHz Clock
6.5
9.5
20
mW max BUF Bit = 0. Gain = 32 or 128 @ fCLK IN = 2.4576 MHz
mW max BUF Bit = 1. Gain = 32 or 128 @ fCLK IN = 2.4576 MHz
Standby (Power-Down) Current20
Standby (Power-Down) Current20
µA max
µA max
External MCLK IN = 0 V or DVDD. Typically 10 µA. VDD = +5 V
External MCLK IN = 0 V or DVDD. Typically 5 µA. VDD = +3.3 V
10
NOTES
1Temperature Range as follows: A Version, –40°C to +85°C.
2A calibration is effectively a conversion so these errors will be of the order of the conversion noise shown in Tables V to XII. This applies after calibration at the
temperature of interest.
3Recalibration at any temperature will remove these drift errors.
4Positive Full-Scale Error includes Zero-Scale Errors (Unipolar Offset Error or Bipolar Zero Error) and applies to both unipolar and bipolar input ranges.
5Full-Scale Drift includes Zero-Scale Drift (Unipolar Offset Drift or Bipolar Zero Drift) and applies to both unipolar and bipolar input ranges.
6Gain Error does not include Zero-Scale Errors. It is calculated as Full-Scale Error–Unipolar Offset Error for unipolar ranges and Full-Scale Error–Bipolar Zero Error
for bipolar ranges.
7Gain Error Drift does not include Unipolar Offset Drift/Bipolar Zero Drift. It is effectively the drift of the part if zero scale calibrations only were performed.
8These numbers are guaranteed by design and/or characterization.
9This common-mode voltage range is allowed provided that the input voltage on AIN(+) or AIN(–) does not go more positive than A VDD + 30 mV or go more nega-
tive than AGND – 30 mV.
10The analog input voltage range on AIN(+) is given here with respect to the voltage on AIN(–). The absolute voltage on the analog inputs should not go more posi-
tive than AVDD + 30 mV or go more negative than AGND – 30 mV.
11
V
= REF IN(+) – REF IN(–).
REF
12These logic output levels apply to the MCLK OUT only when it is loaded with one CMOS load.
13Sample tested at +25°C to ensure compliance.
14After calibration, if the analog input exceeds positive full scale, the converter will output all 1s. If the analog input is less than negative full scale, then the device will
output all 0s.
15These calibration and span limits apply provided the absolute voltage on the analog inputs does not exceed AVDD + 30 mV or go more negative than AGND –
30 mV. The offset calibration limit applies to both the unipolar zero point and the bipolar zero point.
16Assumes CLK Bit of Setup Register is set to correct status corresponding to the master clock frequency.
17When using a crystal or ceramic resonator across the MCLK pins as the clock source for the device, the DVDD current and power dissipation will vary depending on
the crystal or resonator type (see Clocking and Oscillator Circuit section).
18Measured at dc and applies in the selected passband. PSRR at 50 Hz will exceed 120 dB with filter notches of 25 Hz or 50 Hz. PSRR at 60 Hz will exceed 120 dB
with filter notches of 20 Hz or 60 Hz.
19PSRR depends on gain. Gain of 1: 85 dB typ; Gain of 2: 90 dB typ; Gains of 32 and 128: 95 dB typ.
20If the external master clock continues to run in standby mode, the standby current increases to 50 µA typical. When using a crystal or ceramic resonator across the
MCLK pins as the clock source for the device, the internal oscillator continues to run in standby mode and the power dissipation depends on the crystal or
resonator type (see Standby Mode section).
Specifications subject to change without notice.
–4–
REV. C
ADI [ ADI ]
