AD7715–SPECIFICATIONS
(AV
A
Pa
rameter
SYSTEM CALIBRATION
Positive Full-Scale Calibration Limit
14
Negative Full-Scale Calibration Limit
14
Offset Calibration Limit
15
Input Span
15
POWER REQUIREMENTS
Power Supply Voltages
AV
DD
Voltage (AD7715-3)
AV
DD
Voltage (AD7715-5)
DV
DD
Voltage
Power Supply Currents
AV
DD
Current
A Version
= +3 V to +5 V, DV
DD
= +3 V to +5 V, REF IN(+) = +1.25 V (AD7715-3) or +2.5 V
(AD7715-5); REF IN(–) = AGND; MCLK IN = 1 MHz to 2.4576 MHz unless otherwise noted. All specifications T
MIN
to T
MAX
unless otherwise noted.)
DD
Unit
V max
V max
V max
V min
V max
Conditions/Comments
GAIN Is the Selected PGA Gain (1, 2, 32 or 128)
GAIN Is the Selected PGA Gain (1, 2, 32 or 128)
GAIN Is the Selected PGA Gain (1, 2, 32 or 128)
GAIN Is the Selected PGA Gain (1, 2, 32 or 128)
GAIN Is the Selected PGA Gain (1, 2, 32 or 128)
(1.05
×
V
REF
)/GAIN
–(1.05
×
V
REF
)/GAIN
–(1.05
×
V
REF
)/GAIN
0.8
×
V
REF
/GAIN
(2.1
×
V
REF
)/GAIN
+3 to +3.6
+4.75 to +5.25
+3 to +5.25
V
V
V
For Specified Performance
For Specified Performance
For Specified Performance
AV
DD
= 3.3 V or 5 V. Gain = 1 to 128 (f
CLK IN
= 1 MHz) or
Gain = 1 or 2 (f
CLK IN
= 2.4576 MHz)
Typically 0.2 mA. BUF Bit of Setup Register = 0
Typically 0.4 mA. BUF Bit of Setup Register = 1
AV
DD
= 3.3 V or 5 V. Gain = 32 or 128 (f
CLK IN
= 2.4576 MHz)
16
Typically 0.3 mA. BUF Bit of Setup Register = 0
Typically 0.8 mA. BUF Bit of Setup Register = 1
Digital I/Ps = 0 V or DV
DD
. External MCLK IN
Typically 0.15 mA. DV
DD
= 3.3 V. f
CLK IN
= 1 MHz
Typically 0.3 mA. DV
DD
= 5 V. f
CLK IN
= 1 MHz
Typically 0.4 mA. DV
DD
= 3.3 V. f
CLK IN
= 2.4576 MHz
Typically 0.6 mA. DV
DD
= 5 V. f
CLK IN
= 2.4576 MHz
AV
DD
= DV
DD
= +3.3 V. Digital I/Ps = 0 V or DV
DD
. External MCLK IN
BUF Bit = 0. All Gains 1 MHz Clock
BUF Bit = 1. All Gains 1 MHz Clock
BUF Bit = 0. Gain = 32 or 128 @ f
CLK IN
= 2.4576 MHz
BUF Bit = 1. Gain = 32 or 128 @ f
CLK IN
= 2.4576 MHz
AV
DD
= DV
DD
= +5 V. Digital I/Ps = 0 V or DV
DD
. External MCLK IN
BUF Bit = 0. All Gains 1 MHz Clock
BUF Bit = 1. All Gains 1 MHz Clock
BUF Bit = 0. Gain = 32 or 128 @ f
CLK IN
= 2.4576 MHz
BUF Bit = 1. Gain = 32 or 128 @ f
CLK IN
= 2.4576 MHz
External MCLK IN = 0 V or DV
DD
. Typically 10
µA.
V
DD
= +5 V
External MCLK IN = 0 V or DV
DD
. Typically 5
µA.
V
DD
= +3.3 V
0.27
0.6
0.5
1.1
DV
DD
Current
17
0.18
0.4
0.5
0.8
See Note 19
1.5
2.65
3.3
5.3
Normal-Mode Power Dissipation
17
3.25
5
6.5
9.5
20
10
mA max
mA max
mA max
mA max
mA max
mA max
mA max
mA max
dB typ
mW max
mW max
mW max
mW max
mW max
mW max
mW max
mW max
µA
max
µA
max
Power Supply Rejection
18
Normal-Mode Power Dissipation
17
Standby (Power-Down) Current
20
Standby (Power-Down) Current
20
NOTES
1
Temperature Range as follows: A Version, –40°C to +85°C.
2
A calibration is effectively a conversion so these errors will be of the order of the conversion noise shown in Tables V to XII. This applies after calibration at the
temperature of interest.
3
Recalibration at any temperature will remove these drift errors.
4
Positive Full-Scale Error includes Zero-Scale Errors (Unipolar Offset Error or Bipolar Zero Error) and applies to both unipolar and bipolar input ranges.
5
Full-Scale Drift includes Zero-Scale Drift (Unipolar Offset Drift or Bipolar Zero Drift) and applies to both unipolar and bipolar input ranges.
6
Gain Error does not include Zero-Scale Errors. It is calculated as Full-Scale Error–Unipolar Offset Error for unipolar ranges and Full-Scale Error–Bipolar Zero Error
for bipolar ranges.
7
Gain Error Drift does not include Unipolar Offset Drift/Bipolar Zero Drift. It is effectively the drift of the part if zero scale calibrations only were performed.
8
These numbers are guaranteed by design and/or characterization.
9
This common-mode voltage range is allowed provided that the input voltage on AIN(+) or AIN(–) does not go more positive than A V
DD
+ 30 mV or go more nega-
tive than AGND – 30 mV.
10
The analog input voltage range on AIN(+) is given here with respect to the voltage on AIN(–). The absolute voltage on the analog inputs should not go more posi-
tive than AV
DD
+ 30 mV or go more negative than AGND – 30 mV.
11
V
REF
= REF IN(+) – REF IN(–).
12
These logic output levels apply to the MCLK OUT only when it is loaded with one CMOS load.
13
Sample tested at +25°C to ensure compliance.
14
After calibration, if the analog input exceeds positive full scale, the converter will output all 1s. If the analog input is less than negative full scale, then the device will
output all 0s.
15
These calibration and span limits apply provided the absolute voltage on the analog inputs does not exceed AV
DD
+ 30 mV or go more negative than AGND –
30 mV. The offset calibration limit applies to both the unipolar zero point and the bipolar zero point.
16
Assumes CLK Bit of Setup Register is set to correct status corresponding to the master clock frequency.
17
When using a crystal or ceramic resonator across the MCLK pins as the clock source for the device, the DV
DD
current and power dissipation will vary depending on
the crystal or resonator type (see Clocking and Oscillator Circuit section).
18
Measured at dc and applies in the selected passband. PSRR at 50 Hz will exceed 120 dB with filter notches of 25 Hz or 50 Hz. PSRR at 60 Hz will exceed 120 dB
with filter notches of 20 Hz or 60 Hz.
19
PSRR depends on gain. Gain of 1: 85 dB typ; Gain of 2: 90 dB typ; Gains of 32 and 128: 95 dB typ.
20
If the external master clock continues to run in standby mode, the standby current increases to 50
µA
typical. When using a crystal or ceramic resonator across the
MCLK pins as the clock source for the device, the internal oscillator continues to run in standby mode and the power dissipation depends on the crystal or
resonator type (see Standby Mode section).
Specifications subject to change without notice.
–4–
REV. C
AD [ ANALOG DEVICES ]
