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AD7715AN-5 参数 Datasheet PDF下载

AD7715AN-5图片预览
型号: AD7715AN-5
PDF下载: 下载PDF文件 查看货源
内容描述: 3 V / 5 V , 450 uA的16位, Σ-Δ ADC [3 V/5 V, 450 uA 16-Bit, Sigma-Delta ADC]
分类和应用: 转换器模数转换器光电二极管
文件页数/大小: 31 页 / 476 K
品牌: AD [ ANALOG DEVICES ]
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AD7715-5–SPECIFICATIONS
(AV
f
= 2.4576 MHz unless otherwise noted. All specifications T
CLK IN
= +5 V, DV
DD
= +3 V or +5 V, REF IN(+) = +2.5 V; REF IN(–) = AGND;
MIN
to T
MAX
unless otherwise noted.)
DD
Parameter
STATIC PERFORMANCE
No Missing Codes
Output Noise
Integral Nonlinearity
Unipolar Offset Error
Unipolar Offset Drift
3
Bipolar Zero Error
Bipolar Zero Drift
3
Positive Full-Scale Error
4
Full-Scale Drift
3, 5
Gain Error
6
Gain Drift
3, 7
Bipolar Negative Full-Scale Error
2
Bipolar Negative Full-Scale Drift
3
ANALOG INPUTS/REFERENCE INPUTS
Input Common-Mode Rejection (CMR)
Normal-Mode 50 Hz Rejection
8
Normal-Mode 60 Hz Rejection
8
Common-Mode 50 Hz Rejection
8
Common-Mode 60 Hz Rejection
8
Common-Mode Voltage Range
9
Absolute AIN/REF IN Voltage
8
Absolute/Common-Mode AIN Voltage
9
AIN DC Input Current
8
AIN Sampling Capacitance
8
AIN Differential Voltage Range
10
AIN Input Sampling Rate, f
S
REF IN(+) – REF IN(–) Voltage
REF IN Input Sampling Rate, f
S
LOGIC INPUTS
Input Current
All Inputs Except MCLK IN
V
INL
, Input Low Voltage
V
INL
, Input Low Voltage
V
INH
, Input High Voltage
V
INH
, Input High Voltage
MCLK IN Only
V
INL
, Input Low Voltage
V
INL
, Input Low Voltage
V
INH
, Input High Voltage
V
INH
, Input High Voltage
LOGIC OUTPUTS (Including MCLK OUT)
V
OL
, Output Low Voltage
V
OL
, Output Low Voltage
V
OH
, Output High Voltage
V
OH
, Output High Voltage
Floating State Leakage Current
Floating State Output Capacitance
13
Data Output Coding
A Version
1
16
See Tables V to VIII
±0.0015
See Note 2
0.5
See Note 2
0.5
See Note 2
0.5
See Note 2
0.5
±0.0015
1
0.6
90
98
98
150
150
AGND to AV
DD
AGND – 30 mV
AV
DD
+ 30 mV
AGND + 50 mV
AV
DD
– 1.5 V
1
10
0 to +V
REF
/GAIN
11
±V
REF
/GAIN
GAIN
×
f
CLK IN
/64
f
CLK IN
/8
+2.5
f
CLK IN
/64
±10
0.8
0.4
2.4
2.0
0.8
0.4
3.5
2.5
0.4
0.4
4.0
DV
DD
– 0.6 V
±10
9
Binary
Offset Binary
Unit
Bits min
% of FSR max
µV/°C
typ
µV/°C
typ
µV/°C
typ
Conditions/Comments
Guaranteed by Design. Filter Notch
60 Hz
Depends on Filter Cutoffs and Selected Gain
Filter Notch
60 Hz
ppm of FSR/°C typ
% of FSR max
Typically
±0.0004%
µV/°C
typ
For Gains of 1 and 2
µV/°C
typ
For Gains of 32 and 128
dB min
dB min
dB min
dB min
dB min
V min to V max
V min
V max
V min
V max
nA max
pF max
nom
nom
Specifications for AIN and REF IN Unless Noted
at DC. Typically 102 dB
For Filter Notches of 25 Hz, 50 Hz,
±
0.02
×
f
NOTCH
For Filter Notches of 20 Hz, 60 Hz,
±
0.02
×
f
NOTCH
For Filter Notches of 25 Hz, 50 Hz,
±
0.02
×
f
NOTCH
For Filter Notches of 20 Hz, 60 Hz,
±
0.02
×
f
NOTCH
AIN for BUF Bit of Setup Register = 0 and REF IN
AIN for BUF Bit of Setup Register = 0 and REF IN
BUF Bit of Setup Register = 1
V nom
Unipolar Input Range (B/U Bit of Setup Register = 1)
Bipolar Input Range (B/U Bit of Setup Register = 0)
For Gains of 1 and 2
For Gains of 32 and 128
±1%
for Specified Performance. Functional with
Lower V
REF
µA
max
V max
V max
V min
V min
V max
V max
V min
V min
V max
V max
V min
V min
µA
max
pF typ
DV
DD
= +5 V
DV
DD
= +3.3 V
DV
DD
= +5 V
DV
DD
= +5 V
DV
DD
= +3.3 V
DV
DD
= +5 V
DV
DD
= +3.3 V
I
SINK
= 800
µA
Except for MCLK OUT
12
. DV
DD
= +5 V
I
SINK
= 100
µA
Except for MCLK OUT
12
. DV
DD
= +3.3 V
I
SOURCE
= 200
µA
Except for MCLK OUT
12
. DV
DD
= +5 V
I
SOURCE
= 100
µA
Except for MCLK OUT
12
. DV
DD
= +3.3 V
Unipolar Mode
Bipolar Mode
–2–
REV. C