AD73360
Table VII. Control Register A Description
7
6
5
4
3
2
1
0
CONTROL REGISTER A
RESET
DC2
DC1
DC0
SLB
–
MM
DATA/PGM
Bit Name
Description
0
1
2
3
4
5
6
7
DATA/PGM Operating Mode (0 = Program; 1 = Data Mode)
MM
Reserved
Mixed Mode (0 = OFF; 1 = Enabled)
Must Be Programmed to Zero (0)
SLB
DC0
SPORT Loop-Back Mode (0 = OFF; 1 = Enabled)
Device Count (Bit 0)
DC1
DC2
Device Count (Bit 1)
Device Count (Bit 2)
RESET
Software Reset (0 = OFF; 1 = Initiates Reset)
Table VIII. Control Register B Description
7
6
5
4
3
2
1
0
CONTROL REGISTER B
CEE
MCD2
MCD1
MCD0
SCD1
SCD0
DR1
DR0
Bit Name
Description
0
1
2
3
4
5
6
7
DR0
DR1
Decimation Rate (Bit 0)
Decimation Rate (Bit 1)
Serial Clock Divider (Bit 0)
Serial Clock Divider (Bit 1)
Master Clock Divider (Bit 0)
Master Clock Divider (Bit 1)
Master Clock Divider (Bit 2)
SCD0
SCD1
MCD0
MCD1
MCD2
CEE
Control Echo Enable (0 = OFF; 1 = Enabled)
Table IX. Control Register C Description
7
6
5
4
3
2
1
0
CONTROL REGISTER C
5VEN
RU
PUREF
–
–
–
–
GPU
Bit Name
Description
0
1
2
3
4
5
6
7
GPU
Global Power-Up Device (0 = Power Down; 1 = Power Up)
Must Be Programmed to Zero (0)
Must Be Programmed to Zero (0)
Must Be Programmed to Zero (0)
Must Be Programmed to Zero (0)
REF Power (0 = Power Down; 1 = Power Up)
REFOUT Use (0 = Disable REFOUT; 1 = Enable REFOUT)
Enable 5 V Operating Mode (0 = Disable 5 V Mode;
1 = Enable 5 V Mode)
Reserved
Reserved
Reserved
Reserved
PUREF
RU
5VEN
REV. B
–15–
ADI [ ADI ]
