AD73360
Decimation Rate Divider
Master Clock Divider
The AD73360 features a programmable decimation rate divider
that allows users flexibility in matching the AD73360’s ADC
sample rates to the needs of the DSP software. The maximum
sample rate available is DMCLK/256 and the other available
rates are: DMCLK/512, DMCLK/1024 and DMCLK/2048.
The slowest rate (DMCLK/2048) is the default sample rate.
The sample rate divider is programmable by setting bits CRB:0-1.
Table XVII shows the sample rate corresponding to the various
bit settings.
The AD73360 features a programmable master clock divider
that allows the user to reduce an externally available master
clock, at pin MCLK, by one of the ratios 1, 2, 3, 4 or 5 to pro-
duce an internal master clock signal (DMCLK) that is used to
calculate the sampling and serial clock rates. The master clock
divider is programmable by setting CRB:4-6. Table XV shows
the division ratio corresponding to the various bit settings. The
default divider ratio is divide-by-one.
Table XV. DMCLK (Internal) Rate Divider Settings
Table XVII. Decimation Rate Divider Settings
MCD2
MCD1
MCD0
DMCLK Rate
DR1
DR0
Sample Rate
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
MCLK
0
0
1
1
0
1
0
1
DMCLK/2048
DMCLK/1024
DMCLK/512
DMCLK/256
MCLK/2
MCLK/3
MCLK/4
MCLK/5
MCLK
MCLK
MCLK
OPERATION
General Description
The AD73360 inputs and outputs data in a Time Division
Multiplexing (TDM) format. When data is being read from the
AD73360 each channel has a fixed time slot in which its data is
transmitted. If a channel is not powered up, no data is transmit-
ted during the allocated time slot and the SDO line will be
three-stated. When the AD73360 is first powered up or reset it
will be set to Program Mode and will output an SDOFS. After a
reset the SDOFS will be asserted once every sample period
(125 µs assuming 16.384 MHz master clock). If the AD73360 is
configured in Frame Sync Loop-Back Mode, one control word
can be transmitted after each SDOFS pulse. Figure 10a shows
the SDO and SDOFS lines after a reset. The serial data sent by
SDO will not contain valid ADC data until the AD73360 is put
into Data Mode or Mixed Mode. Control Registers D through
F allow channels to be powered up individually. This gives
greater flexibility and control over power consumption. Figure
10b shows the SDOFS and SDO of the AD73360 when all
channels are powered up and Figure 10c shows SDOFS and
SDO with channels 1, 3 and 5 powered up.
Serial Clock Rate Divider
The AD73360 features a programmable serial clock divider that
allows users to match the serial clock (SCLK) rate of the data to
that of the DSP engine or host processor. The maximum SCLK
rate available is DMCLK and the other available rates are:
DMCLK/2, DMCLK/4 and DMCLK/8. The slowest rate
(DMCLK/8) is the default SCLK rate. The serial clock divider
is programmable by setting bits CRB:2–3. Table XVI shows the
serial clock rate corresponding to the various bit settings.
Table XVI. SCLK Rate Divider Settings
SCD1
SCD0
SCLK Rate
0
0
1
1
0
1
0
1
DMCLK/8
DMCLK/4
DMCLK/2
DMCLK
1/F
SAMPLE
SE
SDOFS
SDO
Figure 10a. Output Timing After Reset (Program Mode)
SE
SDOFS
SDO
CHANNEL 1 CHANNEL 2 CHANNEL 3 CHANNEL 4 CHANNEL 5 CHANNEL 6
Figure 10b. Output Timing: All Channels Powered Up (Data/Mixed Mode)
SE
SDOFS
CHANNEL 1
CHANNEL 5
CHANNEL 3
SDO
Figure 10c. Output Timing: Channels 1, 3 and 5 Powered Up (Data/Mixed Mode)
REV. B
–19–
ADI [ ADI ]
