AD549
tracter section’s gain for positive and negative inputs matched
over temperature.
Frequency compensation is provided by R11, R12, and C1 and
C2. The bandwidth of the circuit is 300 kHz at input signals
greater than 50 µA, and decreases smoothly with decreasing
signal levels.
To trim the circuit, set the input currents to 10 µA and trim
A3’s offset using the amplifier’s trim potentiometer so the out-
put equals 0. Then set I1 to 1 µA and adjust the output to equal
1 V by trimming R10. Additional offset trims on the amplifiers
A1 and A2 can be used to increase the voltage input accuracy
and dynamic range.
Figure 43. Photodiode Preamp Noise Sources
The very low input current of the AD549 makes this circuit use-
ful over a very wide range of signal currents. The total input
current (which determines the low level accuracy of the circuit)
is the sum of the amplifier input current, the leakage across the
compensating capacitor (negligible if polystyrene or Teflon ca-
pacitor is used), and the collector to collector, and collector to
base leakages of one side of the dual log transistors. The magni-
tude of these last two leakages depend on the amplifier’s input
offset voltage and are typically less than 10 fA with 1 mV offsets.
The low level accuracy is limited primarily by the amplifier’s in-
put current, only 60 fA maximum when the AD549L is used.
Figure 44. Photodiode Preamp Noise Sources’ Spectral
Density vs. Frequency
Log Ratio Amplifier
Logarithmic ratio circuits are useful for processing signals with
wide dynamic range. The AD549L’s 60 fA maximum input cur-
rent makes it possible to build a log ratio amplifier with 1% log
conformance for input current ranging from 10 pA to 1 mA, a
dynamic range of 160 dB.
The log ratio amplifier in Figure 45 provides an output voltage
proportional to the log base 10 of the ratio of the input currents
I1 and I2. Resistors R1 and R2 are provided for voltage inputs.
Since NPN devices are used in the feedback loop of the front-
end amplifiers that provide the log transfer function, the output
is valid only for positive input voltages and input currents. The
input currents set the collector currents IC1 and IC2 of a
matched pair of log transistors Q1 and Q2 to develop voltages
VA and VB:
VA, B = – (kT/q) ln IC/IES
where IES is the transistors’ saturation current.
The difference of VA and VB is taken by the subtractor section
to obtain:
Figure 45. Log Ratio Amplifier
VC = (kT/q) ln (IC2/IC1)
The effects of the emitter resistance of Q1 and Q2 can degrade
the circuit’s accuracy at input currents above 100 µA. The net-
works composed of R13, D1, R16, and R14, D2, R17 compen-
sate for these errors, so that this circuit has less than 1% log
conformance error at 1 mA input currents. The correct value
for R13 and R14 depends on the type of log transistors used.
49.9 kΩ resistors were chosen for use with LM394 transistors.
Smaller resistance values will be needed for smaller log
transistors.
VC is scaled up by the ratio of (R9 + R10)/R8, which is equal to
approximately 16 at room temperature, resulting in the output
voltage:
V
OUT = 1 × log (IC2/IC1) V.
R8 is a resistor with a positive 3500 ppm/°C temperature coeffi-
cient to provide the necessary temperature compensation. The
parallel combination of R15 and R7 is provided to keep the sub
REV. A
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ADI [ ADI ]
