AD5382
t1
24
24
SCLK
t3
t6
t2
t5
t4
SYNC
DIN
t7
t8 t9
DB0
DB23
t10
t11
t13
BUSY
t12
t17
1
LDAC
t14
1
V
OUT
t15
t13
t17
2
2
LDAC
t16
V
OUT
t18
CLR
t19
V
OUT
1
2
LDAC ACTIVE DURING BUSY
LDAC ACTIVE AFTER BUSY
Figure 3. Serial Interface Timing Diagram (Standalone Mode)
SCLK
24
48
t7A
SYNC
DIN
DB23
DB0
DB23
DB23
DB0
INPUT WORD SPECIFIES
REGISTER TO BE READ
NOP CONDITION
DB0
SDO
UNDEFINED
SELECTED REGISTER
DATA CLOCKED OUT
Figure 4. Serial Interface Timing Diagram (Data Readback Mode)
t1
SCLK
24
48
t3
t2
t21
t7
t22
t4
SYNC
DIN
t8 t9
DB23
DB0 DB23
DB0
INPUT WORD FOR DAC N
INPUT WORD FOR DAC N+1
t20
DB23
DB0
SDO
UNDEFINED
INPUT WORD FOR DAC N
t13
t23
LDAC
Figure 5. Serial Interface Timing Diagram (Daisy-Chain Mode)
Rev. 0 | Page 9 of 40
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