AD5382
I
2
C SERIAL INTERFACE
Table 7. DV
DD
= 2.7 V to 5.5 V; AV
DD
= 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications
T
MIN
to T
MAX
, unless otherwise noted
Parameter
F
SCL
t
1
t
2
t
3
t
4
t
5
t
63
t
7
t
8
t
9
t
10
t
11
Limit at T
MIN
, T
MAX
400
2.5
0.6
1.3
0.6
100
0.9
0
0.6
0.6
1.3
300
0
300
0
300
20 + 0.1C
b 4
400
Unit
kHz max
µs min
µs min
µs min
µs min
ns min
µs max
µs min
µs min
µs min
µs min
ns max
ns min
ns max
ns min
ns max
ns min
pF max
Description
SCL clock frequency
SCL cycle time
t
HIGH
, SCL high time
t
LOW
, SCL low time
t
HD,STA
, start/repeated start condition hold time
t
SU,DAT
, data setup time
t
HD,DAT
, data hold time
t
HD,DAT
, data hold time
t
SU,STA
, setup time for repeated start
t
SU,STO
, stop condition setup time
t
BUF
, bus free time between a STOP and a START condition
t
R
, rise time of SCL and SDA when receiving
t
R
, rise time of SCL and SDA when receiving (CMOS compatible)
t
F
, fall time of SDA when transmitting
t
F
, fall time of SDA when receiving (CMOS compatible)
t
F
, fall time of SCL and SDA when receiving
t
F
, fall time of SCL and SDA when transmitting
Capacitive load for each bus line
C
b
1
2
Guaranteed by design and characterization, not production tested.
See Figure 6.
3
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V
IH
min of the SCL signal) in order to bridge the undefined region of
SCL’s falling edge.
4
C
b
is the total capacitance, in pF, of one bus line. t
R
and t
F
are measured between 0.3 DV
DD
and 0.7 DV
DD
.
SDA
t
9
t
3
t
10
t
11
t
4
SCL
t
4
START
CONDITION
t
6
t
2
t
5
t
7
REPEATED
START
CONDITION
t
1
t
8
STOP
CONDITION
03731-0-007
Figure 6. I2C Compatible Serial Interface Timing Diagram
Rev. 0 | Page 10 of 40
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