AD5382
TIMING CHARACTERISTICS
SPI, QSPI, MICROWIRE, OR DSP COMPATIBLE SERIAL INTERFACE
Table 6. DVDD= 2.7 V to 5.5 V ; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications
TMIN to TMAX, unless otherwise noted
Parameter1, 2, 3
Limit at TMIN, TMAX
Unit
Description
t1
t2
t3
t4
33
13
13
13
13
33
10
50
5
4.5
30
670
20
20
100
0
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns max
ns min
ns min
µs typ
ns min
µs max
ns max
ns min
ns min
ns min
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
24th SCLK falling edge to SYNC falling edge
Minimum SYNC low time
4
t5
4
t6
t7
Minimum SYNC high time
t7A
t8
t9
Minimum SYNC high time in Readback mode
Data setup time
Data hold time
24th SCLK falling edge to BUSY falling edge
BUSY pulse width low (single channel update)
24th SCLK falling edge to LDAC falling edge
LDAC pulse width low
4
t10
t11
4
t12
t13
t14
t15
t16
t17
t18
t19
BUSY rising edge to DAC output response time
BUSY rising edge to LDAC falling edge
LDAC falling edge to DAC output response time
DAC output settling time
100
8
20
35
20
5
CLR pulse width low
CLR pulse activation time
5
t20
t21
SCLK rising edge to SDO valid
SCLK falling edge to SYNC rising edge
SYNC rising edge to SCLK rising edge
SYNC rising edge to LDAC falling edge
5
5
t22
8
t23
20
1 Guaranteed by design and characterization, not production tested.
2 All input signals are specified with tr = tf = 5 ns (10% to 90% of VCC) and are timed from a voltage level of 1.2 V.
3 See Figure 2, Figure 3, Figure 4, and Figure 5.
4 Standalone mode only.
5 Daisy-chain mode only.
200µA
I
I
OL
V
V
(MIN) OR
(MAX)
OH
OL
TO OUTPUT PIN
C
L
50pF
200µA
OH
Figure 2. Load Circuit for SDO Timing Diagram
(Serial Interface, Daisy-Chain Mode)
Rev. 0 | Page 8 of 40
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