AD5382
PARALLEL INTERFACE
Table 8. DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications
TMIN to TMAX, unless otherwise noted
Parameter1,2,3
Limit at TMIN, TMAX
Unit
Description
t0
t1
t2
t3
t4
t5
t6
t7
t8
4.5
4.5
20
20
0
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns max
ns min
ns min
ns min
µs typ
ns min
µsmax
REG0, REG1, address to WR rising edge setup time
REG0, REG1, address to WR rising edge hold time
CS pulse width low
WR pulse width low
CS to WR falling edge setup time
WR to CS rising edge hold time
Data to WR rising edge setup time
Data to WR rising edge hold time
WR pulse width high
0
4.5
4.5
20
700
30
670
30
20
100
20
0
4
t9
Minimum WR cycle time (single-channel write)
WR rising edge to BUSY falling edge
BUSY pulse width low (single-channel update)
WR rising edge to LDAC falling edge
LDAC pulse width low
4
t10
4, 5
t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
BUSY rising edge to DAC output response time
LDAC rising edge to WR rising edge
BUSY rising edge to LDAC falling edge
LDAC falling edge to DAC output response time
DAC output settling time
100
8
20
35
CLR pulse width low
CLR pulse activation time
1 Guaranteed by design and characterization, not production tested.
2 All input signals are specified with tR = tR = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.2 V.
3 See Figure 7.
4 See Figure 29.
5 Measured with the load circuit of Figure 2.
Rev. 0 | Page 11 of 40
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