AD1847
Miscellaneous Infor m ation Register (Index Addr ess 12)
IA3:0
D ata 7
D ata 6
D ata 5
D ata 4
D ata 3
D ata 2
D ata 1
D ata 0
1100
FRS
T SSEL
res
res
res
res
res
res
The Miscellaneous Information Register can only be changed when the AD1847 is in the Mode Change Enable (MCE) state. Changes to this
register are updated at the next Serial Data Frame Sync (SDFS) boundary. If FRS is LO (i.e., 32 slots per frame), and either TSSEL or FRS
change in the first sample of a frame, the change is not updated at the second sample of the same frame, but at the first sample of the next frame.
T SSEL
T ransmit Slot Select. T his bit determines which T DM time slots the AD1847 should transmit on.
0
1
T ransmit on time slots 3, 4 and 5. Used when SDI and SDO are tied together (i.e., “1-wire” system).
T ransmit on slots 0, 1 and 2. Used when SDI and SDO are independent inputs and outputs
(i.e., “2-wire” system).
FRS
res
Frame Size. T his bit selects the number of time slots per frame.
0
1
Selects 32 slots per frame (two samples per frame sync or frame sync at half the sample rate).
Selects 16 slots per frame (one sample per frame sync or frame sync at the sample rate).
Reserved for future expansion. Write zeros (LO) to all reserved bits.
T his register’s initial state after reset is: 0000 0000 (00h).
D igital Mix Contr ol Register (Index Addr ess 13)
IA3:0
D ata 7
D ata 6
D ata 5
D ata 4
D ata 3
D ata 2
D ata 1
D ata 0
1101
DMA5
DMA4
DMA3
DMA2
DMA1
DMA0
res
D M E
DME
Digital Mix Enable. T his bit enables the digital mix of the ADCs’ output with the DACs’ input. When enabled, the data
from the ADCs is digitally mixed with other data being delivered to the DACs (regardless of whether or not playback
[PEN] is enabled, i.e., set). If there is a capture overrun, then the last sample captured before overrun will be used for
the digital mix. If playback is enabled (PEN set) and there is a playback underrun, then a midscale zero will be added to
the digital mix data.
0
1
Digital mix disabled (muted)
Digital mix enabled
DMA5:0 Digital Mix Attenuation. T hese bits determine the attenuation of the ADC output data mixed with the DAC input data.
T he least significant bit of this 64-level attenuate select represents –1.5 dB. Maximum attenuation is –94.5 dB.
res
Reserved for future expansion. Write zeros (LO) to all reserved bits.
T his register’s initial state after reset is: 0000 0000 (00h).
Invalid Addr ess (Index Addr ess 14)
IA3:0
D ata 7
D ata 6
D ata 5
D ata 4
D ata 3
D ata 2
D ata 1
D ata 0
1110
inval
inval
inval
inval
inval
inval
inval
inval
inval
Writes to this index address are ignored. Index readback of this index address will return the Status Word.
Invalid Addr ess (Index Addr ess 15)
IA3:0
D ata 7
D ata 6
D ata 5
D ata 4
D ata 3
D ata 2
D ata 1
D ata 0
1111
inval
inval
inval
inval
inval
inval
inval
inval
inval
Writes to this index address are ignored. Index readback of this index address will return the Status Word.
REV. B
–17–
ADI [ ADI ]
