AD1847
Left Auxiliar y # 2 Input Contr ol Register (Index Addr ess 4)
IA3:0
D ata 7
D ata 6
D ata 5
D ata 4
D ata 3
D ata 2
D ata 1
D ata 0
0100
LMX2
res
res
LX2G 4
LX2G 3
LX2G 2
LX2G 1
LX2G 0
LX2G4:0 Left Auxiliary # 2 Gain Select. T he least significant bit of this 32-level gain/attenuate select represents –1.5 dB.
LX2G4:0 = 0 produces a +12 dB gain. LX2G4:0 = “01000” (8 decimal) produces 0 dB gain. Maximum attenuation is
–34.5 dB. Gains referred to 2.0 V p-p full-scale output level.
res
Reserved for future expansion. Write zeros (LO) to all reserved bits.
LMX2
Left Auxiliary # 2 Mute. T his bit, when set HI, will mute the left channel of the Auxiliary # 2 input source. T his bit is HI
after reset.
T his register’s initial state after reset is: 1000 0000 (80h).
Right Auxiliar y # 2 Input Contr ol Register (Index Addr ess 5)
IA3:0
D ata 7
D ata 6
D ata 5
D ata 4
D ata 3
D ata 2
D ata 1
D ata 0
0101
RMX2
res
res
RX2G 4
RX2G 3
RX2G 2
RX2G 1
RX2G 0
RX2G4:0 Right Auxiliary # 2 Gain Select. T he least significant bit of this 32-level gain/attenuate select represents –1.5 dB.
RX2G4:0 = 0 produces a +12 dB gain. RX2G4:0 = “01000” (8 decimal) produces 0 dB gain. Maximum attenuation is
–34.5 dB. Gains referred to 2.0 V p-p full-scale output level.
res
Reserved for future expansion. Write zeros (LO) to all reserved bits.
RMX2
Right Auxiliary # 2 Mute. T his bit, when set HI, will mute the right channel of the Auxiliary # 2 input source. T his bit is
HI after reset.
T his register’s initial state after reset is: 1000 0000 (80h).
Left D AC Contr ol Register (Index Addr ess 6)
IA3:0
D ata 7
D ata 6
D ata 5
D ata 4
D ata 3
D ata 2
D ata 1
D ata 0
0110
LD M
res
LD A5
LD A4
LD A3
LD A2
LD A1
LD A0
LDA5:0 Left DAC Attenuate Select. T he least significant bit of this 64-level attenuate select represents –1.5 dB. LDA5:0 = 0 pro-
duces a 0 dB attenuation. Maximum attenuation is –94.5 dB.
res
Reserved for future expansion. Write zeros (LO) to all reserved bits.
LDM
Left DAC Mute. T his bit, when set HI, will mute the left channel output. Auxiliary inputs are muted independently with
the Left Auxiliary Input Control Registers. T his bit is HI after reset.
T his register’s initial state after reset is: 1000 0000 (80h).
Right D AC Contr ol Register (Index Addr ess 7)
IA3:0
D ata 7
D ata 6
D ata 5
D ata 4
D ata 3
D ata 2
D ata 1
D ata 0
0111
RDM
res
RDA5
RDA4
RDA3
RDA2
RDA1
RDA0
RDA5:0 Right DAC Attenuate Select. T he least significant bit of this 64-level attenuate select represents –1.5 dB. RDA5:0 = 0
produces a 0 dB attenuation. Maximum attenuation must be at least –94.5 dB.
res
Reserved for future expansion. Write zeros (LO) to all reserved bits.
RDM
Right DAC Mute. T his bit, when set HI, will mute the right DAC output. Auxiliary inputs are muted independently with
the Right Auxiliary Input Control Registers. T his bit is HI after reset.
T his register’s initial state after reset is: 1000 0000 (80h).
–14–
REV. B
ADI [ ADI ]
