AD1847
IA3:0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
D ata 7
LSS1
RSS1
LMX1
RMX1
LMX2
RMX2
LD M
RDM
res
D ata 6
LSS0
RSS0
res
D ata 5
res
D ata 4
res
D ata 3
LIG 3
RIG 3
LX1G 3
RX1G 3
LX2G 3
RX2G 3
LD A3
RDA3
C FS2
ACAL
res
D ata 2
LIG 2
RIG 2
LX1G 2
RX1G 2
LX2G 2
RX2G 2
LD A2
RDA2
C FS1
res
D ata 1
LIG 1
RIG 1
LX1G 1
RX1G 1
LX2G 1
RX2G 1
LD A1
RDA1
C FS0
res
D ata 0
LIG 0
RIG 0
LX1G 0
RX1G 0
LX2G 0
RX2G 0
LD A0
RDA0
CSL
Index
0
1
res
res
res
LX1G 4
RX1G 4
LX2G 4
RX2G 4
LD A4
RDA4
S/M
2
res
res
3
res
res
4
res
res
5
res
LD A5
RDA5
C/L
6
res
7
FM T
res
8
res
res
res
P EN
9
XC T L1
inval
XC T L0
inval
T SSEL
DMA4
inval
inval
CLKT S
inval
res
res
res
res
res
10
11
12
13
14
15
inval
inval
inval
inval
inval
FRS
res
res
res
res
res
DMA5
inval
DMA3
inval
inval
DMA2
inval
DMA1
inval
DMA0
inval
res
D M E
inval
inval
inval
inval
inval
inval
inval
inval
Figure 9. Register Map Sum m ary
Contr ol Register Mapping Sum m ar y
A detailed map of the control register bit assignments is summa-
rized for reference in Figure 9.
Figure 10 illustrates the connection between master and slave(s)
in a daisy-chained, multiple Codec system. Note that the T SI
pin of the master Codec should be tied to digital ground. T he
XT AL1I pin of the slaves should be connected to digital
ground, and XT AL1O pin should be left unconnected, while
the XT AL2I pin should be connected to the CLKOUT pin of
the AD1847 master, and the XT AL2O pin generates a driven
version of the CLKOUT signal applied to the XT AL2I pin.
D aisy-Chained Multiple Codecs
Multiple AD1847s can be configured in a daisy-chain system
with a single master Codec and one or more slave Codecs.
Codecs in a daisy-chained configuration are synchronized at the
sample level.
T he master and slave AD1847s should be powered-up together.
If this is not possible, the slave(s) should power-up before the
master Codec, such that the slave(s) are ready when the master
starts to drive the serial interface, and a serial data frame sync
(SDFS) can synchronize the master and slave(s).
INITIALIZATIO N AND P RO CED URES
Reset and P ower D own
A total reset of the AD1847 is defined as any event which
requires both the digital and analog section of the AD1847 to
return to a known and stable state. T otal reset mode, as well as
power down, occurs when the PWRDOWN pin of the AD1847
has been asserted low for minimum power consumption. When
the PWRDOWN signal is deasserted, the AD1847 must be cali-
brated by setting the ACAL bit and exiting from the Mode
Change Enable (MCE) state.
T he sample rate for the master and slave(s) should be pro-
grammed together. If this is not possible, the slave(s) should be
programmed before the master AD1847. A slave AD1847 enters
a time-out period after a new sample rate has been selected.
During this time-out period, a slave will ignore any activity on
the SDFS signal (i.e., frame syncs). T here is no software means
to determine when a slave has exited from this time-out period
and is ready to respond to frame syncs. However, as long as the
AD1847 master is driving the serial interface, a frame sync will
not occur before the slave Codec(s) are ready.
T he reset occurs, and only resets the digital section of the
AD1847, when the RESET pin of the AD1847 has been as-
serted LO to initialize all registers to known values. See the reg-
ister definitions for the exact values initialized. T he register reset
defaults include T SSEL = 0 (1-wire system) and FRS = 0
(32 slots per frame). If the target application requires a 2-wire
system design or 16 slots per frame, the AD1847 can be
bootstrapped into these configurations.
Note that the time slots for all slave AD1847s must be assigned
to those slots which immediately follow the time slots consumed
by the master AD1847 so that the T SO (T ime Slot Output)/T SI
(T ime Slot Input) signaling operates properly. For example, in a
2-wire system with one master and one slave, the time slot as-
signment should be 0, 1, 2 (16, 17, 18) for the master AD1847,
and 3, 4, 5 (19, 20, 21) for the slave AD1847.
–20–
REV. B
ADI [ ADI ]
