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AD1847JP 参数 Datasheet PDF下载

AD1847JP图片预览
型号: AD1847JP
PDF下载: 下载PDF文件 查看货源
内容描述: 串行端口16位SoundPort立体声编解码器 [Serial-Port 16-Bit SoundPort Stereo Codec]
分类和应用: 解码器编解码器商用集成电路
文件页数/大小: 28 页 / 313 K
品牌: ADI [ ADI ]
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AD1847  
Inter face Configur ation Register (Index Addr ess 9)  
IA3:0  
D ata 7  
D ata 6  
D ata 5  
D ata 4  
D ata 3  
D ata 2  
D ata 1  
D ata 0  
1001  
res  
res  
res  
res  
ACAL  
res  
res  
P EN  
PEN  
Playback Enable. T his bit will enable the playback of data in the format selected. PEN may be set and reset without  
setting the MCE bit.  
0
1
Playback Disabled  
Playback Enabled  
ACAL  
Autocalibrate Enable. T his bit determines whether the AD1847 performs an autocalibrate when exiting from the Mode  
Change Enable (MCE) state. If the ACAL bit is not set, the previous autocalibration values are used when returning from  
the Mode Change Enable (MCE) state and no autocalibration takes place. Autocalibration must be preformed after initial  
power-up for proper operation. T his bit is HI after reset.  
0
1
No autocalibration  
Autocalibration allowed  
NOT E: T he ACAL bit can only be changed when the AD1847 is in the Mode Change Enable (MCE) state.  
res  
Reserved for future expansion. Write zeros (LO) to all reserved bits.  
T his register’s initial state after reset is: 0000 1000 (08h).  
P in Contr ol Register (Index Addr ess 10)  
IA3:0  
D ata 7  
D ata 6  
D ata 5  
D ata 4  
D ata 3  
D ata 2  
D ata 1  
D ata 0  
1010  
XC T L1  
XC T L0  
CLKT S  
res  
res  
res  
res  
res  
CLKT S Clock T hree-State. If the BM bit is HI, and the CLKT S bit is HI, then the CLKOUT pin will be three-stated. If the BM  
bit is HI, and the bit CLKT S is LO, then the CLKOUT pin is not three-stated. If the BM bit is LO, then the CLKOUT  
pin is always three-stated.  
XCT L1:0 External Control. T he state of these independent bits is reflected on the respective XCT L1 and XCT L0 pins of the  
AD1847.  
0
1
T T L logic LO on XCT L1, XCT L0 pins  
T T L logic HI on XCT L1, XCT L0 pins  
res  
Reserved for future expansion. Write zeros (LO) to all reserved bits.  
T his register’s initial state after reset is: 0000 0000 (00h).  
Invalid Addr ess (Index Addr ess 11)  
IA3:0  
D ata 7  
D ata 6  
D ata 5  
D ata 4  
D ata 3  
D ata 2  
D ata 1  
D ata 0  
1011  
inval  
inval  
inval  
inval  
inval  
inval  
inval  
inval  
inval  
Writes to this index address are ignored. Index readback of this index address will return the Status Word.  
–16–  
REV. B  
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