AD1847
MCE bit set HI, IA3:0 = “1100” to address the Miscellaneous
Information Index Register, and DAT A7:0 = “1X00 0000” to
set the FRS bit HI.
24.576
MHz
16.9344
MHz
2
2
T he host CPU or DSP must maintain the MCE bit set HI in
slot 16, which is the Control Word of the second sample of
the frame, so that the AD1847 does not initiate autocalibration
prematurely. At the next frame sync, the AD1847 will be
reconfigured.
XTAL1I,O XTAL2I,O
SCLK
TSI
SDFS
AD1847
(MASTER)
SDI
SDO
TSO
CLKOUT
T he AD1847 must be reset after power up. When the RESET
signal is deasserted, the AD1847 will autocalibrate when the
MCE bit is reset LO (i.e., when exiting the Mode Change En-
able state) only if the ACAL bit is set. If the ACAL bit is not
set, the previous autocalibration values will be used.
TSI
XTAL2I
SCLK
SDFS
SDI
XTAL1O
XTAL2O
N/C
(SLAVE 1)
XTAL1I
SDO
T he AD1847 will not function properly unless an auto-
calibration is performed after power up.
TSO
During power down, the serial port digital output pins and the
analog output pins take the following states:
TSI
XTAL2I
SCLK
SDFS
SDI
XTAL1O
XTAL2O
N/C
SCLK–LO if BM is HI (i.e., bus master), input pin if BM is
LO (i.e., bus slave)
SDFS–LO if BM is HI, input pin if BM is LO
SDO–three-state
(SLAVE 2)
XTAL1I
SDO
TSO
T SO–three-state
CLKOUT –LO if BM HI, three-state if BM is LO
V
REF–pulled to analog ground
Figure 10a. One-Wire Daisy-Chained Codec Interconnect
L_OUT , R_ OUT – pulled to analog ground
24.576
MHz
16.9344
MHz
Clock Connections and Clock Rates
When the AD1847 is configured as a bus slave (BM = LO), the
XT AL1I pin should be connected to digital ground, and the
XT AL2I pin should be tied to the CLKOUT of the AD1847
bus master. T he XT AL1O and the XT AL2O pins should be left
unconnected. When the AD1847 is configured as a bus master
(BM = HI), the XT AL1I and the XT AL1O pin should be con-
nected to a 24.576 MHz crystal, and the XT AL2I and
XT AL2O pin should be connected to a 16.9344 MHz crystal.
2
2
XTAL1I, O XTAL2I, O
SCLK
TSI
SDFS
AD1847
(MASTER)
SDI
SDO
TSO
CLKOUT
When XT AL1 is selected (by resetting the CSL bit LO in the
Data Format Register) as the clock source, the SCLK pin will
generated a serial clock at 12.288 MHz (or one half of the crys-
tal frequency applied at XT AL1), and the CLKOUT pin will
also generate a clock output at 12.288 MHz when the AD1847
is in bus master mode (BM = HI). When XT AL2 is selected (by
setting the CSL bit HI in the Data Format Register) as the clock
source, the SCLK pin will generate a serial clock at 11.2896 MHz
(or two thirds of the crystal frequency applied at XT AL2), and
the CLKOUT pin will generate a clock output at 16.9344 MHz
when the AD1847 is in bus master mode (BM = H I). The
CLKOUT pin will be three-stated when the AD1847 is placed
in bus slave mode (BM = LO).
TSI
XTAL2I
SCLK
SDFS
SDI
XTAL1O
XTAL2O
N/C
(SLAVE 1)
XTAL1I
SDO
TSO
TSI
XTAL2I
SCLK
SDFS
SDI
XTAL1O
XTAL2O
N/C
(SLAVE 2)
XTAL1I
SDO
TSO
When the selected frame size is 32 slots per frame (by resetting
the FRS bit LO in the Miscellaneous Information Register), the
SDFS pin will generate a serial data frame sync at the frequency
of the selected sample rate divided by two, when the AD1847 is
in bus master mode (BM = HI). When the selected frame size is
16 slots per frame (by setting the FRS bit HI in the Miscella-
neous Information Register), the SDFS pin will generate a serial
data frame sync at the frequency of the selected sample rate,
when the AD1847 is in bus master mode (BM = HI).
Figure 10b. Two-Wire Daisy-Chained Codec Interconnect
T o bootstrap into T SSEL = 1 (i.e., 2-wire system design), the
host CPU or DSP must transmit to the AD1847 in slot 0 a
Control Word with the MCE bit set HI, IA3:0 = “1100” to
address the Miscellaneous Information Index Register, and
DAT A7:0 = “X100 000” to set the T SSEL bit HI. T o bootstrap
into FRS = 1 (i.e., 16 slots per frame), the host CPU or DSP
must transmit to the AD1847 in slot 0 a Control Word with the
REV. B
–21–
ADI [ ADI ]
