AD1846
ISA BUS
BCLK
D MA Tim ing
Below, timing parameters are shown for 8-Bit Mono Sample
Read/Capture and Write/Playback DMA transfers in Figures 13
and 14. Note that in single-channel DMA mode, the Read/
Capture cycle timing shown in Figure 13 applies to the PDRQ
and PDAK signals, rather than the CDRQ and CDAK signals
as shown. T he same timing parameters apply to multibyte trans-
fers. T he relationship between timing signals is shown in Fig-
ures 15 and 16.
PDRQ
OUTPUT
tDRHD
tDKSU
PDAK
INPUT
tDKHDA
tDBDL
T he Host Interrupt Pin (INT ) will go HI during the sample pe-
riod in which the Current Count Register underflows. T his
event is referenced to the internal sample period clock which is
not available externally.
DBEN
OUTPUTS
DBDIR
OUTPUT
HI
ISA BUS
BCLK
tSTW
WR INPUT
CDRQ OUTPUT
tWDSU
tDHD2
tDRHD
DATA7:0
INPUTS
tDKSU
CDAK INPUT
Figure 14. 8-Bit Mono DMA Write/Playback Cycle
tDKHDB
ISA BUS
BCLK
tDBDL
DBEN & DBDIR
OUTPUTS
CDRQ/
PDRQ
OUTPUTS
tSTW
RD INPUT
CDAK/
tRDDV
tDHD1
PDAK
INPUTS
DATA7:0
OUTPUTS
tBWDN
RD OR WR
INPUTS
Figure 13. 8-Bit Mono DMA Read/Capture Cycle
RIGHT/HIGH
BYTE
LEFT/LOW
BYTE
DATA7:0
Figure 15. 8-Bit Stereo or 16-Bit Mono DMA Cycle
ISA BUS
BCLK
CDRQ/ PDRQ
OUTPUTS
CDAK/ PDAK
INPUTS
tBWDN
RD OR WR
INPUTS
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
DATA7:0
LEFT SAMPLE
RIGHT SAMPLE
Figure 16. 16-Bit Stereo DMA Cycle
REV. A
–23–
ADI [ ADI ]
