AD14060/AD14060L
Synchr onous Read/Wr ite —Bus Slave
T he bus master must meet these (bus slave) timing requirements.
Use these specifications for bus master accesses of a slave’s IOP
registers or internal memory (in multiprocessor memory space).
5 V
3.3 V
P aram eter
Min
Max
Min
Max
Units
Timing Requirements:
tSADRI
tHADRI
tSRWLI
tHRWLI
tRWHPI
tSDAT WH
tHDAT WH
Address, SW Setup Before CLKIN
15.5 + DT /2
9.5 + 5DT /16
–3.5 – 5DT /16 8 + 7DT /16
3
15.5 + DT /2
9.5 + 5DT /16
–3.5 – 5DT /16 8 + 7DT /16
3
ns
ns
ns
ns
ns
ns
ns
Address, SW Hold Before CLKIN
RD/WR Low Setup Before CLKIN1
RD/WR Low Hold After CLKIN
RD/WR Pulse High
Data Setup Before WR High
Data Hold After WR High
4.5 + DT /2
4.5 + DT /2
5.5
1.5
5.5
1.5
Switching Characteristics:
tSDDAT O
tDAT T R
tDACKAD
tACKT R
Data Delay After CLKIN
20 + 5DT /16
8 – DT /8
10
20 + 5DT /16
8 – DT /8
10
ns
ns
ns
ns
Data Disable After CLKIN2
ACK Delay After Address, SW3
ACK Disable After CLKIN3
0 – DT /8
0 – DT /8
–1 – DT /8
7 – DT /8
–1 – DT /8
7 – DT /8
NOT ES
1tSRWLI (min) = 9.5 + 5DT /16 when Multiprocessor Memory Space Wait State (MMSWS bit in WAIT register) is disabled; when MMSWS is enabled,
tSRWLI (min) = 4 + DT /8.
2See System Hold T ime Calculation under T est Conditions for calculation of hold times given capacitive and dc loads.
3tDACKAD is true only if the address and SW inputs have setup times (before CLKIN) greater than 10.5 + DT/8 and less than 18.5 + 3DT/4. If the address and SW inputs have
setup times greater than 19 + 3DT /4, then ACK is valid 15 + DT /4 (max) after CLKIN. A slave that sees an address with an M field match will respond with ACK
regardless of the state of MMSWS or strobes. A slave will three-state ACK every cycle with t ACKT R
.
CLKIN
tSADRI
tHADRI
ADDRESS
SW
tDACKAD
tACKTR
ACK
READ ACCESS
tSRWLI
tHRWLI
tRWHPI
RD
tSDDATO
tDATTR
DATA
(OUT)
WRITE ACCESS
tRWHPI
tSRWLI
tHRWLI
WR
tHDATWH
tSDATWH
DATA
(IN)
Figure 17. Synchronous Read/Write —Bus Slave
REV. A
–22–
ADI [ ADI ]
