AD14060/AD14060L
Multipr ocessor Bus Request and H ost Bus Request
Use these specifications for passing of bus mastership between
multiprocessing ADSP-2106x’s (BRx) or a host processor
(HBR, HBG).
5 V
3.3 V
P aram eter
Min
Max
Min
Max
Units
Timing Requirements:
tHBGRCSV HBG Low to RD/WR/CS Valid1
19.5 + 5DT/4
13.5 + 3DT/4
5.5 + DT/2
19.5 + 5DT/4 ns
tSHBRI
tHHBRI
tSHBGI
tHHBGI
tSBRI
HBR Setup Before CLKIN2
20 + 3DT/4
13 + DT/2
13 + DT/2
20 + 3DT/4
20 + 3DT/4
13 + DT/2
13 + DT/2
20 + 3DT/4
ns
13.5 + 3DT/4 ns
ns
HBR Hold Before CLKIN2
HBG Setup Before CLKIN
HBG Hold Before CLKIN High
BRx, CPA Setup Before CLKIN3
BRx, CPA Hold Before CLKIN High
RPBA Setup Before CLKIN
RPBA Hold Before CLKIN
5.5 + DT/2
ns
ns
ns
ns
tHBRI
5.5 + DT/2
5.5 + DT/2
tSRPBAI
tHRPBAI
11.5 + 3DT/4
11.5 + 3DT/4 ns
Switching Characteristics:
tDHBGO
tHHBGO
tDBRO
HBG Delay After CLKIN
HBG Hold After CLKIN
BRx Delay After CLKIN
BRx Hold After CLKIN
CPA Low Delay After CLKIN
CPA Disable After CLKIN
8 – DT/8
8 – DT/8
8 – DT/8
8 – DT/8
ns
ns
ns
ns
ns
ns
ns
ns
ns
–2 – DT/8
–2 – DT/8
tHBRO
–2 – DT/8
–2 – DT/8
tDCPAO
tTRCPA
tDRDYCS
tTRDYHG
tARDYTR
9 – DT/8
5.5 – DT/8
9.5
9 – DT/8
5.5 – DT/8
10.25
–2 – DT/8
–2 – DT/8
REDY (O/D) or (A/D) Low from CS and HBR Low4
REDY (O/D) Disable or REDY (A/D) High from HBG4
REDY (A/D) Disable from CS or HBR High4
44 + 27DT/16
44 + 27DT/16
11
11
NOT ES
1For first asynchronous access after HBR and CS asserted, ADDR31–0 must be a non-MMS value 1/2 tCK before RD or WR goes low or by tHBGRCSV after HBG goes
low. T his is easily accomplished by driving an upper address signal high when HBG is asserted.
2Only required for recognition in the current cycle.
3CPA assertion must meet the setup to CLKIN; deassertion does not need to meet the setup to CLKIN.
4(O/D) = open drain, (A/D) = active drive.
REV. A
–23–
ADI [ ADI ]
