ACT88430QJ-T
Rev 1.0, 24-Oct-2018
bit GPIO_OUT = 0 to configure GPIO as an input. When
using GPIO as an output, GPIO_OUT = 0 configures it
as an open drain output, and GPIO_OUT = 1 configures
it as a logic low output. When used as either an input
or an output, I2C bit GPIO_STAT always provides the
real-time status of the GPIO pin. GPIO_STAT = 0 when
GPIO pin is a logic 0. GPIO_STAT = 1 when GPIO pin
is a logic 1.
the internal POK signals they immediately assert. They
follow a programmed delay when de-asserted. The
nRESET_AUX1 delay time is controlled by the I2C bits
RST_AUX1_DLY[2:0], which programs the delay be-
tween 400us and 2mS in 227us steps. The nRE-
SET_AUX2 delay time is controlled by the I2C bits
RST_AUX2_DLY[2:0], which programs the delay be-
tween 200us and 1ms in 114us steps. These pins can
also be used as inputs to control different power rail en-
able signals. They are configurable, so refer to the back
of the datasheet for their specific functionality for each
CMI. Contact the factory for available options. They are
open drain outputs and are 5.5V tolerant meaning that
they can be pulled up to 5.5V even if VIO_IN is less than
5.5V.
GPIO pin is referenced to the VIN pin, and is 5.5V toler-
ant meaning that GPIO can go to 5.5V even if VIN is
less than 5.5V.
IRQ
The IRQ pin is an output that issues an interrupt to the
host CPU/Controller when an ACT88430 fault or warn-
ing condition occurs.
nRESET
IRQ is triggered by:
nRESET issues the main reset to the CPU/controller.
nRESET is immediately asserted low when either the
VIN voltage is above or below the UV or OV thresholds
or any valid output supply voltage is below its Power
Good (POK) threshold. After startup, nRESET de-as-
serts after a programmable delay time after all outputs
are above their respective UVLO thresholds. The nRE-
SET delay time is controlled by the I2C bits
nRST_DLY[2:0], which programs the delay between
200us and 1ms in 114us steps. nRESET is configura-
ble, so refer to the CMI Options section in the back of
the datasheet for its specific functionality for each CMI.
nRESET is an open drain output and is 5.5V tolerant
meaning that nRESET can be pulled up to 5.5V even if
VIO_IN is less than 5.5V.
Die temperature exceeding Thermal Interrupt Threshold
of 135C.
Any buck regulator reaching peak current limit, ILIMSET,
for 16 cycles after softstart.
Any LDO regulator reaching current limit, LDOx_ILIM,
for more than 16us after softstart.
BUCK1 PMOS switch exceeding Current Detection
threshold 75% of ILIMSET when system is configured
in bypass mode.
IRQ is masked by the I2C register 0x00h bit2
(IRQ_nMASK) by default to mask all IRQ conditions. To
enable IRQ functionality, set IRQ_nMASK = 1. IRQ is
an active-low open drain 5.5V compatible output.
EXT_EN
EXT_EN is used to control an external regulator or to
provide a control signal to other system components.
When the MODE pin = 0 to configure Buck1 as a stand-
ard power supply, EXT_EN is the output of the
ACT88430’s internal BUCK1 enable signal. When the
MODE pin = 1 to configure Buck1 as a bypass switch,
EXT_EN is the output of the bypass switch enable sig-
nal.
POK
POK indicates that the voltage on the VIN pin is inside
the POK UV and OV Interrupt Thresholds. If the VIN
voltage is above or below these values, POK pulls low
to interrupt the host CPU/Controller. POK is masked by
the I2C bit POK_nMASK by default. To enable POK
functionality, set I2C bit POK_nMASK = 1. I2C bits
POK_OV and POK_UV provide real-time UV and OV
status, even when POK is masked. The POK UV and
OV threshold are configurable via the I2C bits
POK_UV_SET and POK_OV_SET.
The I2C bit EXT_EN_POL controls the EXT_EN polarity.
EXT_EN is active high when EXT_EN_POL is low and
EXT_EN is active low when EXT_EN_POL is high.
EXT_EN is a push-pull CMOS output using VIO_IN sup-
ply. Note that the EXT_EN output is enabled and valid
in all modes of operation. EXT_EN is configurable, so
refer to the CMI Options section in the back of the
datasheet for its specific functionality for each CMI.
POK is an open drain output and is 5.5V tolerant mean-
ing that POK can be pulled up to 5.5V even if VIO_IN is
less than 5.5V.
nRESET_AUX1 and nRESET_AUX2
nRESET_AUX1 and nRESET_AUX2 pins can be used
to signal that the IC is in the SLEEP state or that the
input voltage is above or below the UV or OV threshold.
They can also be tied to one or a combination of the
power supply’s internal POK signals. When asserted by
EXT_EN is referenced to the VIO_IN pin. It should not
be pulled higher than VIO_IN.
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