ACT88430QJ-T
Rev 1.0, 24-Oct-2018
put regulates to the voltage programmed in the I2C reg-
ister Bx_VSET0. During DVS, each output regulates to
Bx_VSET1. The output transitions from Bx_VSET0 to
Bx_VSET1 at a rate determined by the output capaci-
tance and the load current. The outputs transition be-
tween VSET1 and VSET0 by the rate determined by the
I2C bits SLEW.
Compensation
The buck converters utilize current-mode control and a
proprietary internal compensation scheme to simultane-
ously simplify external component selection and opti-
mize transient performance over their full operating
range. No compensation design is required; simply fol-
low a few simple guide lines described below when
choosing external components.
For fault free operation, the user must ensure output
load conditions plus the current required to charge the
output capacitance during a DVS rising voltage condi-
tion does not exceed the current limit setting of the reg-
ulator. As with any power supply, changing an output
voltage too fast can require a current higher than the
current limit setting. The user must ensure that the volt-
age step, slew rate, and load current conditions do not
result in an instantaneous loading that results in a cur-
rent limit condition.
Minimum On-Time
The ACT88430 minimum on-time is 120ns. If the calcu-
lated on-time is less than 120ns with 2.25MHz operation,
then the user must configure the output to switch at
1.125MHz. Setting I2C bits Bx_HalfFreq = 0 sets Fsw =
2.25MHz. Setting Bx_HalfFreq = 1 sets Fsw =
1.125MHz. The following equation calculates the on-
time.
ꢄꢁꢅꢆ
Enter DVS by programming register 0x00h bit1
(DVS_EN) = 1 and then pulling the EXT_EN pin high.
Note that some CMI configurations may not require
DVS_EN = 1 and may use different input pins.
ꢀꢁꢂ
ꢃ
ꢄ
∗ ꢈ
ꢉꢊ
ꢇꢂ
Where Vout is the output voltage, Vin is the input voltage,
and FSW is the switching frequency.
Bx_VSET0 must be higher than Bx_VSET1.
PWR_GOOD, OV, and ILIM are automatically masked
during DVS transitions to avoid asserting nRESET.
BUCK1 Bypass Switch
The ACT88430 provides a bypass mode for 3.3V sys-
tems. This allows the 3.3V input voltage to power the
ACT88430 regulators and also be sequenced to the
downstream loads. In bypass mode, the Buck1 P-ch
FET acts as a switch and the N-ch FET is disabled. The
bypass switch turns on the 3.3V rail with the pro-
grammed delay and softstart time.
Optimizing Noise
Each buck converter contains several features available
via I2C to further optimize functionality. The top P-ch
FET’s turn-on timing can be shifted 100ns from the mas-
ter clock edge via the PHASE_DELAY I2C bit. It can also
be aligned to the rising or falling clock edge via the
PHASE I2C bit. The internal FET rise and fall times can
be optimized to minimize switching noise at the cost of
lower efficiency via the DRVADJ I2C bit.
In bypass mode, the ACT88430 I2C registers are recon-
figured to the following.
1. B1_PWR_GOOD register bit reconfigured to
the output of the Soft Start ramp. When soft
start is complete, this bit goes high to allow the
sequencing of the other regulators to continue.
B1_PWR_GOOD no longer reports the Buck1
output voltage status. It stays high as long as
the bypass switch is enabled.
Overcurrent and Short Circuit Protection
Each buck converter provides overcurrent and short cir-
cuit protection. Overcurrent protection is achieved with
cycle-by-cycle current limiting. The peak current thresh-
old is set by the Bx_ILIM I2C bits. If the peak current
reaches the programmed threshold for 16 consecutive
switching cycles, the IC asserts IRQ low. A short circuit
condition that results in the peak switch current being
122% of Bx_ILIMSET immediately shuts down all sup-
plies, asserts IRQ low and restarts the system in 100ms.
If a buck converter reaches overcurrent or short circuit
protection, the status is reported in the ILIM_REG[x] I2C
registers. The contents of these registers are latched
until read via I2C. Overcurrent and short circuit condi-
tions can be masked via the I2C bit Bx_ILIM_FLTMSK.
2. B1_ILIM bit is the output of the internal PMOS
Current Detection circuit. This is set to 3A typi-
cal. If the bypass current exceeds the Internal
PMOS Current Detection current, B1_ILIM trig-
gers an IRQ output and gets latched in the
ILIM_REG[0] if configured by the IRQ_nMASK.
The B1_ILIM can also be masked with the
B1_ILIM_FLTMSK register.
B1_UV register bit reconfigured to the output of the In-
ternal PMOS Current Shutdown circuit. This is set to 6A
typical. If the bypass switch current exceeds 6A, limits
the current which triggers an under voltage fault condi-
Innovative PowerTM
www.active-semi.com
Copyright © 2016-2018 Active-Semi, Inc.
ActiveSwitcherTM is a trademark of Active-Semi.
I2CTM is a trademark of NXP
33
ACTIVE-SEMI [ ACTIVE-SEMI, INC ]
