ACT5880
Rev 2, 03-Sep-13
REGISTER AND BIT DESCRIPTIONS CONT’D
DEFAULT
and
ACCESS
ADDRESS
and BIT
BLOCK
NAME
DESCRIPTION
Set bit to 0 to enable the TSC ADC block, set bit to 1 to disable it.
7
6
nEN
1
0
W/R
W/R
Set bit to 1 for one channel only acquisition, set bit to 0 for multi-
channel scanning.
SINGLE
Specify which channel to measure for one channel only
acquisition.
W/R Channel[2:0]=0 for X-coordinate position, 1 for Y-coordinate
position, 2 for Z-coordinate position 1, 3 for Z-coordinate position
2, 4 for AUX0, 5 for AUX1, 6 for AUX2 and 7 for AUX3.
5
4
3
CHANNEL[2]
CHANNEL[1]
CHANNEL[0]
0
0
0
Set bit to 1 for scanning channel 0 to channel 3, set bit to 0 for
not scanning. Refer to the REGISTER AND BIT DESCRIPTIONS
section for CHANNEL[2], CHANNEL[1] and CHANNEL[0] for
0xF0
2
CH03
0
W/R
channel coding.
Set bit to 1 for scanning channel 4 to channel 7, set bit to 0 for
not scanning. Refer to the REGISTER AND BIT DESCRIPTIONS
section descriptions for CHANNEL[2], CHANNEL[1] and
CHANNEL[0] for channel coding.
1
0
CH47
ACQ
0
0
W/R
Write and read for different functions. Set bit from 0 to 1
W/R initializes an acquisition procedure designated by the SINGLE,
CHANNEL[2:0] or CH03, CH47.
Data Length of Conversion. Set bit to 0 for 12 bits, set bit to 1 for
8 bits.
7
6
5
CLEN
0
0
W/R
TSC
ADC
Pen Entry Wake-up Enable. Set bit to 1 to allow waking-up
against pen entry.
PENWKEN
PENSTAT
W/R
Pen Touch Detection Instant Status. Read back value is 1 for in
touching, read back value is 0 for no touching.
R
R
Pen Touch Detection Interrupt Status. Read back value is 1 when
a pen touch interrupt is generated and it is automatically cleared
to 0 upon reading. Read back value is 0 when no interrupt is
generated.
4
3
PENIRQ
R
R
R
Data Ready Interrupt Status. Read back value is 1 when the data
ready interrupt is generated and it is automatically cleared to 0
upon reading. Read back value is 0 when no interrupt generated.
DATARDY
R
0xF1
To start a new conversion, this bit must be cleared to 0.
Acquisition Starting Mode Setting.
Set bit to 1 for starting acquisition by when the ACQ bit is set 1.
W/R Set bit to 0 for automatic starting by when pen touch is detected.
The interrupt asserts only when the acquisition completes and
the data is ready.
2
nAUTO
1
Write or read for different functions. Pen Touch Interrupt Mask.
W/R Set bit to 1 to mask the pen touch detection interrupt, set bit to 0
to allow pen touch detection interrupt.
1
0
PENMASK
0
0
Write or read for different functions. Data Ready Interrupt Mask.
W/R Set bit to 1 to mask the data ready interrupt, set bit to 0 to allow
data ready interrupt.
DATAMASK
Note:
W/R: Write and read accessible. R: Read accessible, writing to the bit does not make change to the volume. WE/R: Write
and read accessible, write exact what it is before to avoid unexpected behavior. X is uncertain volume.
www.active-semi.com
Copyright © 2013 Active-Semi, Inc.
Active-Semi Confidential―Do Not Copy or Distribute
ActivePMUTM and ActivePathTM are trademarks of Active-Semi.
I2CTM is a trademark of NXP.
- 37 -