ACT5880
Rev 2, 03-Sep-13
REGISTER AND BIT DESCRIPTIONS CONT’D
DEFAULT
and
ACCESS
ADDRESS
and BIT
BLOCK
NAME
DESCRIPTION
AXU2 data acquisition.
[11] is the MSB.
Full input range is the same as internal reference voltage 2.5V.
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
AXU2[11]
AXU2[10]
AXU2[9]
AXU2[8]
AXU2[7]
AXU2[6]
AXU2[5]
AXU2[4]
AXU2[3]
AXU2[2]
AXU2[1]
AXU2[0]
0
0
0
0
R
0
0xEC
0
0
0
0
AXU2 data acquisition.
[0] is the LSB.
0
R
0
0
0xED
0xEE
0xEF
Not used.
Data reading in those bits is not certain.
x
x
x
TSC
ADC
AXU3 data acquisition.
[11] is the MSB.
Full input range is the same as internal reference voltage 2.5V.
AXU3[11]
AXU3[10]
AXU3[9]
AXU3[8]
AXU3[7]
AXU3[6]
AXU3[5]
AXU3[4]
AXU3[3]
AXU3[2]
AXU3[1]
AXU3[0]
0
0
0
0
0
0
0
0
0
0
0
0
R
AXU3 data acquisition.
[0] is the LSB.
R
x
Not used.
Data reading in those bits is not certain.
x
x
Note:
R: Read accessible, writing to the bit does not make change to the volume. X is uncertain volume.
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