ACT5880
Rev 2, 03-Sep-13
REGISTER AND BIT DESCRIPTIONS CONT’D
DEFAULT
and
ACCESS
ADDRESS
and BIT
BLOCK
NAME
DESCRIPTION
AXU0 data acquisition.
[11] is the MSB.
Full input range is the same as internal reference voltage 2.5V.
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
AXU0[11]
AXU0[10]
AXU0[9]
AXU0[8]
AXU0[7]
AXU0[6]
AXU0[5]
AXU0[4]
AXU0[3]
AXU0[2]
AXU0[1]
AXU0[0]
0
0
0
0
R
0
0xE8
0
0
0
0
AXU0 data acquisition.
[0] is the LSB.
0
R
0
0
0xE9
0xEA
0xEB
Not used.
Data reading in those bits is not certain.
x
x
x
TSC
ADC
AXU1 data acquisition.
[11] is the MSB.
Full input range is the same as internal reference voltage 2.5V.
AXU1[11]
AXU1[10]
AXU1[9]
AXU1[8]
AXU1[7]
AXU1[6]
AXU1[5]
AXU1[4]
AXU1[3]
AXU1[2]
AXU1[1]
AXU1[0]
0
0
0
0
0
0
0
0
0
0
0
0
R
AXU1 data acquisition.
[0] is the LSB.
R
x
Not used.
Data reading in those bits is not certain.
x
x
Note:
R: Read accessible, writing to the bit does not make change to the volume. X is uncertain volume.
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