PLUS
ProASIC
Flash Family FPGAs
Synchronous FIFO Write
WCLKS
Cycle Start
WRB, WBLKB
(Full Inhibits Write)
DI
WPE
FULL
EMPTY
EQTH, GETH
t
, t
t
t
, t
WRCH WBCH
ECBH FCBH
, t
t
, t
ECBA FCBA
WRCS WBCS
t
t
DCS
HCBH
t
t
HCBA
t
WPCH
t
DCH
t
WPCA
t
CMH
CML
t
CCYC
Note: The plot shows the normal operation status.
Figure 1-47 • Synchronous FIFO Write
Table 1-65 • TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/industrial
TJ = –55°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883
Symbol txxx
CCYC
CMH
Description
Min.
7.5
Max. Units
Notes
Cycle time
ns
ns
ns
ns
ns
ns
ns
ns
Clock high phase
3.0
CML
Clock low phase
3.0
DCH
DI hold from WCLKS ↑
DI setup to WCLKS ↑
0.5
DCS
1.0
FCBA
New FULL access from WCLKS ↓
EMPTY↓ access from WCLKS ↓
3.01
3.01
ECBA
ECBH,
FCBH,
HCBH
Old EMPTY, FULL, EQTH, & GETH valid hold
time from WCLKS ↓
1.0
0.5
Empty/full/thresh are invalid from the end of
hold until the new access is complete
HCBA
WPCA
WPCH
EQTH or GETH access from WCLKS ↓
New WPE access from WCLKS ↑
Old WPE valid from WCLKS ↑
4.5
3.0
ns
ns
ns
ns
ns
WPE is invalid, while PARGEN is active
WRCH, WBCH WRB & WBLKB hold from WCLKS ↑
WRCS, WBCS WRB & WBLKB setup to WCLKS ↑
Notes:
0.5
1.0
1. At fast cycles, ECBA and FCBA = MAX (7.5 ns – CMH), 3.0 ns.
2. All –F speed grade devices are 20% slower than the standard numbers.
v5.2
1-71
ACTEL [ Actel Corporation ]
