PLUS
ProASIC
Flash Family FPGAs
FIFO Reset
RESETB
Cycle Start
WRB/RBD1
WCLKS, RCLKS1
FULL
Cycle Start
EMPTY
EQTH, GETH
t
CBRSS
t
, t
t
ERSA FRSA
CBRSH
t
WBRSH
t
THRSA
t
RSL
t
WBRSS
Notes:
1. During rest, the enables (WRB and RBD) must be high OR the clocks (WCLKS and RCKLS) must be low.
2. The plot shows the normal operation status.
Figure 1-48 • FIFO Reset
Table 1-66 • TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/industrial
TJ = –55°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883
Symbol txxx
CBRSH1
CBRSS1
ERSA
Description
WCLKS or RCLKS ↑ hold from RESETB ↑
WCLKS or RCLKS ↓ setup to RESETB ↑
New EMPTY ↑ access from RESETB ↓
FULL ↓ access from RESETB ↓
RESETB low phase
Min.
1.5
1.5
3.0
3.0
7.5
4.5
1.5
1.5
Max.
Units
ns
Notes
Synchronous mode only
Synchronous mode only
ns
ns
FRSA
ns
RSL
ns
THRSA
WBRSH1
WBRSS1
Notes:
EQTH or GETH access from RESETB ↓
WB ↓ hold from RESETB ↑
ns
ns
Asynchronous mode only
Asynchronous mode only
WB ↑ setup to RESETB ↑
ns
1. During rest, the enables (WRB and RBD) must be high OR the clocks (WCLKS and RCKLS) must be low.
2. All –F speed grade devices are 20% slower than the standard numbers.
1-72
v5.2
ACTEL [ Actel Corporation ]
