PLUS
ProASIC
Flash Family FPGAs
Synchronous FIFO Read, Access Timed Output Strobe (Synchronous Transparent)
RCLK
Cycle Start
RDB
RDATA
RPE
Old Data Out
New Valid Data Out (Empty Inhibits Read)
EMPTY
FULL
EQTH, GETH
t
t
t
, t
RDCH
ECBH FCBH
, t
t
ECBA FCBA
RDCS
t
t
THCBH
t
OCH
t
RPCH
HCBA
t
OCA
t
RPCA
t
t
CML
CMH
t
CCYC
Note: The plot shows the normal operation status.
Figure 1-45 • Synchronous FIFO Read, Access Timed Output Strobe (Synchronous Transparent)
Table 1-63 • TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/industrial
TJ = –55°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883
Symbol txxx
CCYC
Description
Min.
7.5
Max. Units
Notes
Cycle time
ns
ns
ns
ns
ns
CMH
Clock high phase
3.0
CML
Clock low phase
3.0
ECBA
New EMPTY access from RCLKS ↓
FULL ↓ access from RCLKS ↓
3.01
3.01
FCBA
ECBH, FCBH, Old EMPTY, FULL, EQTH, & GETH valid hold
1.0
3.0
ns
Empty/full/thresh are invalid from the end
of hold until the new access is complete
THCBH
time from RCLKS ↓
OCA
New DO access from RCLKS ↑
Old DO valid from RCLKS ↑
RDB hold from RCLKS ↑
7.5
ns
ns
ns
ns
ns
ns
ns
OCH
RDCH
RDCS
RPCA
RPCH
HCBA
Notes:
0.5
1.0
9.5
RDB setup to RCLKS ↑
New RPE access from RCLKS ↑
Old RPE valid from RCLKS ↑
EQTH or GETH access from RCLKS ↓
3.0
4.5
1. At fast cycles, ECBA and FCBA = MAX (7.5 ns – CMH), 3.0 ns.
2. All –F speed grade devices are 20% slower than the standard numbers.
v5.2
1-69
ACTEL [ Actel Corporation ]
